# US 10,319,747 B2 · Array substrate, display panel, and display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,747 B2 - Document ID: US10319747B2 - Status: Granted - Kind: B2 - Application number: 15/508,102 - Filed: 2016-07-01 - Published: 2018-10-25 - Granted: 2019-06-11 - Earliest claimed: 2016-01-14 - Assignees: Boe Technology Group Co., Ltd.; Hefei Boe Optoelectronics Technology Co., Ltd. - Applicants: Boe Technology Group Co., Ltd.; Hefei Boe Optoelectronics Technology Co., Ltd. - Inventors: Chuanbao Chen; Jie Yang; Xiaobin Yin - Web page: https://patentgrep.com/patent/US10319747B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/133753: {with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle} - G02F 1/134309: {characterised by their geometrical arrangement} - G02F 1/13624: {having more than one switching element per pixel} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - H10D 30/6729: {characterised by the electrodes} - H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 86/441: {Interconnections, e.g. scanning lines} - G02F 1/13373: {Disclination line; Reverse tilt} - G02F 1/134345: {Subdivided pixels, e.g. for grey scale or redundancy} - G02F 2201/121: common or background - G02F 2201/123: pixel - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract An array substrate includes: a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions; a plurality of data lines; a plurality of gate lines intersecting with the plurality of data lines; and a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions; wherein: each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions. ## Claims ### Claim 1 An array substrate, comprising: a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions of domains of the each sub-pixel; a plurality of data lines; a plurality of gate lines intersecting with the plurality of data lines; and a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions; wherein: each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions; each of the plurality of sub-pixels comprises two pixel electrodes corresponding to the pair of sub-pixel portions; the pair of sub-pixel portions form a dual-domain configuration; the two pixel electrodes are insulated from one another, and have opposite domain tilt directions; the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions; and one gate line is arranged between two rows of sub-pixel portions. ### Claim 2 (depends on 1) The array substrate of claim 1, wherein the pair of transistors are disposed across both the gate line and the data line. ### Claim 3 (depends on 2) The array substrate of claim 2, wherein for each pair of transistors, gate electrodes of the pair of transistors are integrated and are coupled with the gate line; source electrodes of the pair of transistors are disposed over the data line; and drain electrodes of the pair of transistors are respectively disposed at two sides of the data line. ### Claim 4 (depends on 3) The array substrate of claim 3, wherein the drain electrodes of each pair of transistors are respectively coupled with two pixel electrodes diagonally disposed in two neighboring columns of sub-pixel portions. ### Claim 5 (depends on 4) The array substrate of claim 4, wherein the two pixel electrodes diagonally located in two neighboring columns of sub-pixel portions comprise a first pixel electrode on a first row and on an even-numbered column, and a second pixel electrode on a second row and on an odd-numbered column. ### Claim 6 (depends on 4) The array substrate of claim 4, wherein the two pixel electrodes diagonally located in two neighboring pixel units on a same row of pixel units comprises a first pixel electrode on a first row and on an odd-numbered column, and a second pixel electrode on a second row and on an even-numbered column. ### Claim 7 (depends on 1) The array substrate of claim 1, wherein the pair of transistors are disposed across the gate line and at one side of the data line. ### Claim 8 (depends on 7) The array substrate of claim 7, wherein for each pair of transistors, gate electrodes of the pair of transistors are integrated and are coupled with the gate line; source electrodes of the pair of transistors both are disposed over the data line; and drain electrodes of the pair of transistors are respectively disposed at two sides of the gate line and are integrated. ### Claim 9 (depends on 8) The array substrate of claim 8, wherein the drain electrodes of each pair of transistors are respectively coupled with two pixel electrodes in a same column. ### Claim 10 (depends on 1) The array substrate of claim 1, wherein the pair of transistors are disposed across the data line and at one side of the gate line. ### Claim 11 (depends on 10) The array substrate of claim 10, wherein each pair of transistors are configured to control two pixel electrodes located on the one side of the gate line in two neighboring sub-pixel portions on a same row. ### Claim 12 (depends on 1) The array substrate of claim 1, wherein the plurality of data lines are parallel to each other and the plurality of gate lines are parallel to each other. ### Claim 13 (depends on 1) The array substrate of claim 1, further comprising a plurality of common electrode lines disposed in rows and alternating with the plurality of gate lines. ### Claim 14 (depends on 13) The array substrate of claim 13, wherein the plurality of common electrode lines are parallel to each other. ### Claim 15 (depends on 1) The array substrate of claim 1, wherein each pair of transistors are integrally formed. ### Claim 16 (depends on 1) The array substrate of claim 1, wherein the transistors are thin-film transistors (TFTs). ### Claim 17 (depends on 16) The array substrate of claim 16, wherein each TFT further comprises an active layer disposed between a gate electrode layer and a layer of source electrode and drain electrode. ### Claim 18 A display panel, comprising an array substrate including: a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions of domains of the each sub-pixel; a plurality of data lines; a plurality of gate lines intersecting with the plurality of data lines; and a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions; wherein: each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions; each of the plurality of sub-pixels comprises two pixel electrodes corresponding to the pair of sub-pixel portions; the pair of sub-pixel portions form a dual-domain configuration; the two pixel electrodes are insulated from one another, and have opposite domain tilt directions; the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions; and one gate line is arranged between two rows of sub-pixel portions. ### Claim 19 A display apparatus, comprising a display panel having an array substrate, the array substrate comprising: a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions of domains of the each sub-pixel; a plurality of data lines; a plurality of gate lines intersecting with the plurality of data lines; and a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions; wherein: each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions; each of the plurality of sub-pixels comprises two pixel electrodes corresponding to the pair of sub-pixel portions; the pair of sub-pixel portions form a dual-domain configuration; the two pixel electrodes are insulated from one another, and have opposite domain tilt directions; the plurality of data lines alternate with the plurality of columns of sub-pixel portions such that one data line is arranged between two neighboring columns of sub-pixel portions; and one gate line is arranged between two rows of sub-pixel portions.