# US 10,319,738 B2 · Three dimensional semiconductor memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,738 B2 - Document ID: US10319738B2 - Status: Granted - Kind: B2 - Application number: 15/844,188 - Filed: 2017-12-15 - Published: 2018-10-11 - Granted: 2019-06-11 - Earliest claimed: 2017-04-05 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Chang-Bum Kim; Sunghoon Kim - Web page: https://patentgrep.com/patent/US10319738B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 8/14: Word line organisation; Word line lay-out - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/107: {Programming all cells in an array, sector or block to the same state prior to flash erasing} - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10D 89/10: Integrated device layouts - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 8/10: Decoders - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A three-dimensional semiconductor memory device includes a cell string vertically extending from a top surface of a substrate and having first and second cell transistors, first and second word lines connected to gate electrodes of the first and second cell transistors respectively, a first pass transistor connecting the first word line to a row decoder, and a second pass transistor connecting the second word line to the row decoder. The first pass transistor includes a plurality of first sub-transistors connected in parallel between the first word line and the row decoder. ## Claims ### Claim 1 A three-dimensional semiconductor memory device comprising: a cell string vertically extending from a top surface of a substrate and including first and second cell transistors; first and second word lines connected to gate electrodes of the first and second cell transistors, respectively; a first pass transistor connecting the first word line to a row decoder; and a second pass transistor connecting the second word line to the row decoder, wherein the first pass transistor comprises a plurality of first sub-transistors connected in parallel between the first word line and the row decoder. ### Claim 2 (depends on 1) The three-dimensional semiconductor memory device of claim 1, wherein the first sub-transistors each have the same size as that of the second pass transistor. ### Claim 3 (depends on 1) The three-dimensional semiconductor memory device of claim 1, wherein the first sub-transistors have the same gate length and the same gate width. ### Claim 4 (depends on 1) The three-dimensional semiconductor memory device of claim 1, wherein the first sub-transistors have the same gate length and different gate widths. ### Claim 5 (depends on 1) The three-dimensional semiconductor memory device of claim 1, wherein: the first word line is positioned from the top surface of the substrate at a first distance, and the second word line is positioned from the top surface of the substrate at a second distance less than the first distance. ### Claim 6 (depends on 1) The three-dimensional semiconductor memory device of claim 1, wherein the cell string comprises: an electrode structure including a plurality of word lines vertically stacked on the substrate, the plurality of word lines including the first and second word lines; a vertical semiconductor pillar having a width that increases as approaching its top from its bottom and penetrating the electrode structure; and a data storage layer between the electrode structure and the vertical semiconductor pillar. ### Claim 7 (depends on 1) The three-dimensional semiconductor memory device of claim 1, wherein the cell string comprises: a lower electrode structure including a plurality of lower electrodes vertically stacked on the substrate; a lower semiconductor pillar penetrating the lower electrode structure; an upper electrode structure including a plurality of upper electrodes vertically stacked on the lower electrode structure; and an upper semiconductor pillar penetrating the upper electrode structure and connected to the lower semiconductor pillar, wherein each of the lower and upper semiconductor pillars has a width that increases as approaching its top from its bottom, and each of the lower and upper electrode structures comprises the first and second word lines. ### Claim 8 (depends on 1) The three-dimensional semiconductor memory device of claim 1, further comprising: a third cell transistor connected in series to the second cell transistor; a third word line connected to a gate electrode of the third cell transistor; and a third pass transistor connecting the third word line to the row decoder, wherein: the first to third word lines are sequentially stacked on the substrate, and the third pass transistor has a size greater than that of the first pass transistor. ### Claim 9 (depends on 8) The three-dimensional semiconductor memory device of claim 8, wherein: the third pass transistor comprises a plurality of second sub-transistors connected in parallel between the third word line and the row decoder, and a number of the second sub-transistors constituting the third pass transistor being different from that of the first sub-transistors constituting the first pass transistor. ### Claim 10 A three-dimensional semiconductor memory device comprising: a substrate including a peripheral circuit region and a cell array region; an electrode structure including word lines vertically stacked on the substrate of the cell array region, the word lines including a lower word line positioned from a top surface of the substrate at a first distance and an upper word line positioned from the top surface of the substrate at a second distance greater than the first distance; a first pass transistor disposed on the substrate of the peripheral circuit region and connecting a row decoder to the lower word line; and a second pass transistor disposed on the substrate of the peripheral circuit region and connecting the row decoder to the upper word line, wherein the first pass transistor comprises m first sub-transistors connected to the lower word line, and the second pass transistor comprises n second sub-transistors connected to the upper word line, wherein n and m are natural numbers. ### Claim 11 (depends on 10) The three-dimensional semiconductor memory device of claim 10, further comprising: a vertical semiconductor pillar penetrating the electrode structure; and a data storage layer between the electrode structure and the vertical semiconductor pillar, wherein the vertical semiconductor pillar has a width that increases as approaching its top from its bottom. ### Claim 12 (depends on 10) The three-dimensional semiconductor memory device of claim 10, wherein: the first sub-transistors are connected to each other in parallel between the row decoder and the lower word line, and the second sub-transistors are connected to each other in parallel between the row decoder and the upper word line. ### Claim 13 (depends on 10) The three-dimensional semiconductor memory device of claim 10, wherein the first and second sub-transistors have the same gate length and the same gate width. ### Claim 14 (depends on 13) The three-dimensional semiconductor memory device of claim 13, wherein n and m are different natural numbers from each other. ### Claim 15 (depends on 13) The three-dimensional semiconductor memory device of claim 13, wherein the first pass transistor has an effective gate width different from that of the second pass transistor.