# US 10,319,731 B2 · Integrated circuit structure having VFET and embedded memory structure and method of forming same

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- Number: US 10,319,731 B2
- Document ID: US10319731B2
- Status: Granted
- Kind: B2
- Application number: 15/673,548
- Filed: 2017-08-10
- Published: 2019-02-14
- Granted: 2019-06-11
- Earliest claimed: 2017-08-10
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Ruilong Xie; Chun-Chen Yeh; Tenko Yamashita; Kangguo Cheng
- Web page: https://patentgrep.com/patent/US10319731B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/30: characterised by the memory core region
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/43: comprising only one type of peripheral transistor
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/834: {comprising FinFETs}
- H10D 84/837: {comprising vertical IGFETs}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 30/6728: {Vertical TFTs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The disclosure is directed to an integrated circuit structure and method of forming the same. The integrated circuit structure may include: a first device region including: a floating gate structure substantially surrounding a first fin that is over a substrate; a first bottom source/drain within the substrate, and beneath the first fin and the floating gate structure; a first top source/drain over the first fin and the floating gate structure; a first spacer substantially surrounding the first top source/drain and disposed over the floating gate structure; and a gate structure substantially surrounding and insulated from the floating gate structure, the gate structure being disposed over the substrate and having a height greater than a height of the floating gate.

## Claims

### Claim 1

An integrated circuit structure comprising:
a first device region including a vertical flash memory device, the first device region including:
a floating gate structure substantially surrounding a first fin that is over a substrate;
a first bottom source/drain within the substrate, and beneath the first fin and the floating gate structure;
a first top source/drain over the first fin and the floating gate structure;
a first spacer substantially surrounding the first top source/drain and disposed over the floating gate structure; and
a gate structure substantially surrounding and insulated from the floating gate structure, the gate structure being disposed over the substrate and having a height greater than a height of the floating gate, the gate structure having a top surface that is approximately planar with a top surface of the first spacer; and
a second device region including a vertical fin-shaped field effect transistor (VFET), the VFET including:
a VFET gate structure surrounding a second fin that is over the substrate;
a second bottom source/drain within the substrate, and beneath the second fin and the second gate structure;
a second top source/drain over the second fin and the second gate structure; and
a second spacer substantially surrounding the second top source/drain.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the first device region further includes:
a dielectric disposed between the floating gate structure and the gate structure such that the dielectric is laterally adjacent to the gate structure and the floating gate structure, wherein the dielectric is also disposed between the gate structure and the first spacer.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein a sidewall of the floating gate structure extends laterally beyond a sidewall of the first spacer relative to the fin.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the first spacer partially surrounds an upper portion of the fin that is disposed beneath the first top source/drain.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, wherein the first device region further includes:
a dielectric disposed between the floating gate structure and the fin such that the dielectric is laterally adjacent to the floating gate structure and the fin, wherein the dielectric is also disposed between the floating gate structure and a bottom spacer.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1, wherein a sidewall of the VFET gate structure is laterally aligned with a sidewall of the second spacer.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, wherein a top surface of the VFET gate structure is approximately planar with a top surface of the floating gate structure.

### Claim 8 (depends on 1)

The integrated circuit structure of claim 1, wherein the first spacer includes a bilayer of a dielectric material, and wherein the gate structure is free from having the first spacer thereover.

### Claim 9 (depends on 1)

The integrated circuit structure of claim 1, wherein the first device region further includes:
an oxide spacer disposed beneath the floating gate structure, and above the first bottom source/drain and the substrate; and
a nitride spacer disposed beneath the floating gate structure and above the oxide spacer.