# US 10,319,730 B2 · Memory device having a plurality of first conductive pillars penetrating through a stacked film > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,730 B2 - Document ID: US10319730B2 - Status: Granted - Kind: B2 - Application number: 15/927,318 - Filed: 2018-03-21 - Published: 2019-03-28 - Granted: 2019-06-11 - Earliest claimed: 2017-09-22 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Kouji Matsuo - Web page: https://patentgrep.com/patent/US10319730B2 ## CPC - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 20/42: Vias, e.g. via plugs - H10W 90/00: Package configurations - H10W 90/792: {between multiple chips} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A memory device according to an embodiment includes: a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films; a first electrode provided above the stacked film; a second electrode provided above the stacked film; a plurality of first conductive pillars penetrating through the stacked film and having one end electrically connected to the first electrode and another end not connected and positioned below the stacked film; a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films; a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode; a peripheral circuit board provided above the first electrode and the second electrode; a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode; a fourth electrode provided between the second electrode and the peripheral circuit board, the fourth electrode electrically connected to the second electrode; and a transistor electrically connected to the third electrode or the fourth electrode, the transistor provided in the peripheral circuit board. ## Claims ### Claim 1 A memory device comprising: a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films; a first electrode provided above the stacked film; a second electrode provided above the stacked film; a plurality of first conductive pillars penetrating through the stacked film, each of the first conductive pillars having one end electrically connected to the first electrode and another end not connected to the other first conductive pillars, the another end positioned below the stacked film; a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films; a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode; a peripheral circuit board provided above the first electrode and the second electrode; a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode; a fourth electrode provided between the second electrode and the peripheral circuit board, the fourth electrode electrically connected to the second electrode; and a transistor electrically connected to the third electrode or the fourth electrode, the transistor provided in the peripheral circuit board. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein the first conductive pillars are a plurality of gate electrodes. ### Claim 3 (depends on 1) The memory device according to claim 1, wherein an area of one semiconductor film among the semiconductor films is smaller than an area of the other semiconductor films provided below the one semiconductor film. ### Claim 4 (depends on 1) The memory device according to claim 1, further comprising: a first memory cell insulator provided around the first electrode and the second electrode; and a peripheral circuit insulator provided around the third electrode and the fourth electrode, wherein the first electrode, the second electrode, the third electrode, and the fourth electrode contain copper. ### Claim 5 (depends on 4) The memory device according to claim 4, wherein the first memory cell insulator and the peripheral circuit insulator contain silicon oxide, silicon oxynitride, or carbon-added silicon oxide. ### Claim 6 (depends on 4) The memory device according to claim 4, further comprising: a second memory cell insulator, wherein the first memory cell insulator is provided between the second memory cell insulator and the peripheral circuit insulator. ### Claim 7 (depends on 6) The memory device according to claim 6, wherein the second memory cell insulator contains tantalum oxide or aluminum oxide. ### Claim 8 (depends on 1) The memory device according to claim 1, wherein the transistor includes a source portion and a drain portion, and the source portion and the drain portion each contains metal silicide. ### Claim 9 (depends on 8) The memory device according to claim 8, wherein the metal silicide includes titanium silicide, aluminum silicide, nickel silicide, cobalt silicide, tantalum silicide, tungsten silicide, or hafnium silicide. ### Claim 10 (depends on 1) The memory device according to claim 1, wherein the transistor includes a channel portion containing a crystalline semiconductor.