# US 10,319,729 B2 · Methods and apparatuses with vertical strings of memory cells and support circuitry

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- Number: US 10,319,729 B2
- Document ID: US10319729B2
- Status: Granted
- Kind: B2
- Application number: 15/011,819
- Filed: 2016-02-01
- Published: 2016-05-26
- Granted: 2019-06-11
- Earliest claimed: 2014-01-22
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Takehiro Hasegawa; Koji Sakui
- Web page: https://patentgrep.com/patent/US10319729B2

## CPC

- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/49: comprising different types of peripheral transistor
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 88/101: {comprising components on opposite major surfaces of semiconductor substrates}
- G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

## Claims

### Claim 1

A method comprising:
forming openings in a substrate;
forming electrically conductive material in the openings;
forming strings of memory cells on a topside of the substrate;
implanting a plurality of wells in a backside of the substrate;
implanting a plurality of diffusion regions, to be associated with support circuitry, in each of the plurality of wells; and
forming support circuitry on the backside of the substrate on the plurality of wells and associated with the plurality of diffusion regions, wherein the support circuitry is coupled to the strings of memory cells through the electrically conductive material formed in the openings.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the support circuitry comprises using a complementary metal oxide semiconductor (CMOS) fabrication method.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the support circuitry is performed subsequent to forming the strings of memory cells.

### Claim 4

An apparatus comprising:
a substrate having an opening;
an electrically insulative material lining the opening;
an electrically conductive material filling the opening lined with the electrically insulative material; and
a diffusion region in a substantially annular pattern around the opening.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the opening is open on both sides of the substrate.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the diffusion region is a first diffusion region around the opening on a topside of the substrate and further comprising a second diffusion region in a substantially annular pattern around the opening on a backside of the substrate.

### Claim 7 (depends on 4)

The apparatus of claim 4, wherein the diffusion region is a first diffusion region and further comprising:
a second diffusion region implanted in the substrate at a bottom of the opening; and
a metal plug extending from the second diffusion region through the topside of the substrate.

### Claim 8 (depends on 4)

The apparatus of claim 4, wherein the opening comprises an annular ring having a pillar of the substrate in the center of the annular ring and the diffusion region is a first diffusion region around the opening and further comprising a second diffusion region implanted in a top of the pillar.

### Claim 9 (depends on 4)

The apparatus of claim 4, further comprising:
a plurality of strings of memory cells on a first side of the substrate; and
memory support circuitry on a second side of the substrate opposite the first side, wherein the memory support circuitry is coupled to the plurality of strings of memory cells through the electrically conductive material.

### Claim 10

A method comprising:
forming a plurality of surround gate transistors in a substrate by:
forming openings through the substrate that couple a first side of the substrate to an opposite side of the substrate;
lining the openings with an insulative material; and
forming electrically conductive material in the openings;
forming strings of memory cells on the first side of the substrate; and
forming support circuitry on the opposite of the substrate, wherein the support circuitry is coupled to the strings of memory cells through the surround gate transistors.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the openings through the substrate comprises:
forming trenches into the first side of the substrate; and
removing a portion of the substrate to reduce a thickness of the substrate such that the trenches couple the first side to the opposite side.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming a source in the electrically conductive material on the first side of the substrate; and
forming a drain in the electrically conductive material on the opposite side of the substrate.

### Claim 13 (depends on 12)

The method of claim 12, wherein the electrically conductive material is a semiconductor material.

### Claim 14 (depends on 13)

The method of claim 13, wherein the drain is doped into the semiconductor material after removal of the portion of the substrate exposes the semiconductor material on the opposite side.

### Claim 15 (depends on 11)

The method of claim 11, further comprising: forming p-wells or n-wells into the substrate on the first side such that the p-wells or n-wells are exposed on the opposite side of the substrate after removal of the portion of the substrate.