# US 10,319,728 B2 · Fluid ejection devices comprising memory cells

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- Number: US 10,319,728 B2
- Document ID: US10319728B2
- Status: Granted
- Kind: B2
- Application number: 15/379,286
- Filed: 2016-12-14
- Published: 2017-03-30
- Granted: 2019-06-11
- Earliest claimed: 2016-12-14
- Assignees: Hewlett-Packard Development Company, L.P.
- Applicants: Hewlett-Packard Development Company, L.P.
- Inventors: Chaw Sing Ho; Reynaldo V. Villavelez; Xin Ping Cao
- Web page: https://patentgrep.com/patent/US10319728B2

## CPC

- H10B 41/30: characterised by the memory core region
- B41J 2/1433: {Structure of nozzle plates}
- H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/68: Floating-gate IGFETs
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10B: ELECTRONIC MEMORY DEVICES
- B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.

## Claims

### Claim 1

A fluid ejection device comprising:
a substrate; and
a memory cell formed on the substrate and comprising:
a channel region formed in the substrate between a drain region and a source region;
a first dielectric layer over the channel region;
a floating gate capacitively coupled to the channel region through the first dielectric layer, the floating gate comprising a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, wherein the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer;
a third dielectric layer over the floating gate;
a control gate capacitively coupled to the floating gate through the third dielectric layer; and
a dielectric nitride layer between the floating gate and the third dielectric layer to prevent charge loss from the floating gate to the third dielectric layer.

### Claim 2 (depends on 1)

The fluid ejection device of claim 1, wherein the dielectric nitride layer is between the metal layer and the third dielectric layer.

### Claim 3 (depends on 2)

The fluid ejection device of claim 2, wherein the metal layer includes aluminum copper silicon, and the third dielectric layer includes tetraethyl orthosilicate (TEOS).

### Claim 4 (depends on 1)

The fluid ejection device of claim 1, wherein the second dielectric layer includes an un-doped silicon glass layer.

### Claim 5 (depends on 1)

The fluid ejection device of claim 1, wherein the second dielectric layer includes a boron phosphor silicon glass layer.

### Claim 6 (depends on 1)

The fluid ejection device of claim 1, wherein the control gate includes an aluminum copper layer.

### Claim 7 (depends on 1)

The fluid ejection device of claim 1, wherein the memory cell comprises:
a fourth dielectric layer on the control gate, wherein the fourth dielectric layer includes silicon nitride and silicon carbide to protect the memory cell from degradation and provide adhesion to a polymer layer.

### Claim 8 (depends on 1)

The fluid ejection device of claim 1, comprising an array of memory cells, wherein the memory cell is part of the array of memory cells.

### Claim 9 (depends on 8)

The fluid ejection device of claim 8, comprising addressing lines to select access of the memory cells in the array of memory cells.

### Claim 10 (depends on 9)

The fluid ejection device of claim 9, wherein the addressing lines comprise row lines and column lines, and the array of memory cells comprise:
row transistors selectively activatable by the row lines, and
column transistors selectively activatable by the column lines.

### Claim 11 (depends on 1)

The fluid ejection device of claim 1, comprising a printhead die, wherein the substrate and the memory cell is part of the printhead die.

### Claim 12 (depends on 11)

The fluid ejection device of claim 11, wherein the printhead die comprises nozzles to dispense printing fluid.

### Claim 13

A fluid ejection device comprising:
a substrate; and
an array of memory cells on the substrate, wherein a first memory cell of the array of memory cells comprises:
a control gate;
a first dielectric layer under the control gate;
a floating gate capacitively coupled to the control gate through the first dielectric layer, the floating gate comprising a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, wherein the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer;
a third dielectric layer under the floating gate; and
a channel region capacitively coupled to the floating gate through the third dielectric layer and between a drain region and a source region, wherein the drain region overlaps the third dielectric layer a first distance, and the source region overlaps the third dielectric layer a second distance such that an effective length of the channel region between the drain region and the source region is greater than or equal to a sum of the first distance and the second distance.

### Claim 14 (depends on 13)

The fluid ejection device of claim 13, wherein the second dielectric layer includes a boron phosphor silicon glass layer between the polysilicon layer and the metal layer.

### Claim 15 (depends on 13)

The fluid ejection device of claim 13, wherein the second dielectric layer includes an un-doped silicon glass layer between the polysilicon layer and the metal layer.

### Claim 16 (depends on 13)

The fluid ejection device of claim 13, comprising a dielectric nitride layer between the floating gate and the first dielectric layer to prevent charge loss from the floating gate to the first dielectric layer.

### Claim 17 (depends on 13)

The fluid ejection device of claim 13, wherein the array of memory cells comprises row transistors selectively activatable by row address lines, and column transistors selectively activatable by column address lines.

### Claim 18

A printhead comprising:
a substrate; and
a memory cell on the substrate and comprising:
a channel region formed in the substrate between a drain region and a source region;
a first dielectric layer over the channel region;
a floating gate capacitively coupled to the channel region through the first dielectric layer, the floating gate comprising a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, wherein the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer;
a third dielectric layer over the floating gate; and
a control gate capacitively coupled to the floating gate through the third dielectric layer.

### Claim 19 (depends on 18)

The printhead of claim 18, comprising a die including the substrate and the memory cell formed on the substrate.

### Claim 20 (depends on 18)

The printhead of claim 18, wherein the second dielectric layer comprises at least one layer selected from among a boron phosphor silicon glass layer and an un-doped silicon glass layer.