# US 10,319,727 B2 · Fabricating memory devices with optimized gate oxide thickness

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- Number: US 10,319,727 B2
- Document ID: US10319727B2
- Status: Granted
- Kind: B2
- Application number: 15/799,776
- Filed: 2017-10-31
- Published: 2018-05-03
- Granted: 2019-06-11
- Earliest claimed: 2016-10-31
- Assignees: Marvell World Trade Ltd.
- Applicants: Marvell World Trade Ltd.
- Inventors: Runzi Chang; Winston Lee; Peter Lee
- Web page: https://patentgrep.com/patent/US10319727B2

## CPC

- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- G11C 17/165: {Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002)}
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
- H10D 64/514: {characterised by the insulating layers}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 50/283: {by chemical means}
- H10P 76/2041: {Photolithographic processes}
- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.

## Claims

### Claim 1

A method comprising:
exposing respective gate areas of programmable memory devices and processor core devices of an integrated-circuit (IC) die and occluding gate areas of input/output (I/O) devices of the IC die;
etching, from the exposed respective gate areas of the programmable memory devices and the processor core devices, a first layer of oxide material;
forming a second layer of oxide material on the IC die, the second layer of oxide material coating the respective gate areas of the programmable memory devices, the processor core devices, and the I/O devices;
exposing the gate areas of the programmable memory devices and occluding the respective gate areas of the processor core devices and the I/O devices;
etching, from the exposed gate areas of the programmable memory devices, the second layer of oxide material; and
forming a third layer of oxide material on the IC die, the third layer of oxide material coating the respective gate areas of the programmable memory devices, the processor core devices, and the I/O devices of the IC die.

### Claim 2 (depends on 1)

The method of claim 1, wherein a thickness of the third layer of oxide material on the gate areas of the programmable memory devices is less than a combined thickness of the second and third layers of oxide material on the gate areas of the processor core devices.

### Claim 3 (depends on 1)

The method of claim 1, wherein the exposing the respective gate areas of the processor core devices and programmable memory devices of the IC die and occluding gate areas of I/O devices of the IC die comprises depositing a photoresist material, radiating light through a lithography mask, and developing the photoresist material.

### Claim 4 (depends on 3)

The method of claim 3, wherein the photoresist material is a positive photoresist material.

### Claim 5 (depends on 1)

The method of claim 1, wherein the forming of the first layer of oxide material, the second layer of oxide material, or the third layer of oxide material forms a layer of silicon oxynitride material, a layer of silicon dioxide material, or a layer of silicon nitride material.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first, the second, or the third layer of oxide material is formed via chemical vapor deposition across the IC die.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming topographical asperities in the third layer of oxide material at oxide-gate interfaces of the programmable memory devices.