# US 10,319,726 B2 · Semiconductor device

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- Number: US 10,319,726 B2
- Document ID: US10319726B2
- Status: Granted
- Kind: B2
- Application number: 15/642,394
- Filed: 2017-07-06
- Published: 2018-05-10
- Granted: 2019-06-11
- Earliest claimed: 2016-11-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: In Cheol Nam; Sung Hee Han; Dae Sun Kim
- Web page: https://patentgrep.com/patent/US10319726B2

## CPC

- H10B 12/36: {the transistor being a FinFET}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/114: {PN junction isolations}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/662: {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures}
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/50: Isolation regions based on field-effect
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into the element isolation region and penetrating the active region, and a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including an active region and an element isolation region defining the active region;
a gate trench extending into the element isolation region and penetrating the active region; and
a gate structure filling the gate trench and including a first conductivity-type semiconductor layer, a conductive layer, and a second conductivity-type semiconductor layer, sequentially stacked from a lower portion of the gate trench.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first conductivity-type semiconductor layer includes polycrystalline silicon doped with a p-type impurity, and the second conductivity-type semiconductor layer includes polycrystalline silicon doped with an n-type impurity.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the conductive layer includes a metal having a work function value higher than that of the first conductivity-type semiconductor layer and lower than that of the second conductivity-type semiconductor layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising source/drain regions disposed at an upper portion of the active region on opposite sides of the gate trench,
wherein the second conductivity-type semiconductor layer has a region overlapping the source/drain regions, and
wherein the conductive layer does not overlap the source/drain regions.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the gate trench includes a first portion located in the active region and a second portion located in the element isolation region, a depth of the second portion is deeper than a depth of the first portion, and
the gate structure includes a main gate embedded in the first portion and a field pass gate embedded in the second portion.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first conductivity-type semiconductor layer of the main gate has a first thickness in a direction parallel to an upper surface of the substrate fully depleted by a gate voltage in a standby mode, and
the first conductivity-type semiconductor layer of the field pass gate has a second thickness in the direction parallel to an upper surface of the substrate greater than the first thickness.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein an upper surface of the field pass gate is disposed to be lower than an upper surface of the main gate, and
the field pass gate does not overlap the source/drain regions.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, wherein the main gate includes the first conductivity-type semiconductor layer, the conductive layer, and the second conductivity-type semiconductor layer, and
the field pass gate does not include the second conductivity-type semiconductor layer.

### Claim 9 (depends on 5)

The semiconductor device of claim 5, wherein a width of the field pass gate is narrower than a width of the main gate.

### Claim 10 (depends on 4)

The semiconductor device of claim 4, further comprising a data storage element electrically connected to one of the source/drain regions.

### Claim 11

A semiconductor device, comprising:
a substrate including an active region and an element isolation region defining the active region;
a main gate embedded in the active region; and
a field pass gate embedded in the element isolation region,
wherein each of the main gate and the field pass gate includes a first conductivity-type semiconductor layer, a metal layer, and a second conductivity-type semiconductor layer, sequentially stacked from corresponding lower portions of the main gate and the field pass gate.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first conductivity-type semiconductor layer includes polycrystalline silicon doped with a p-type impurity, and
the second conductivity-type semiconductor layer includes polycrystalline silicon doped with an n-type impurity.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the metal layer includes a metal having a work function value higher than that of the first conductivity-type semiconductor layer and lower than that of the second conductivity-type semiconductor layer.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, further comprising source/drain regions disposed at an upper portion of the active region on opposite sides of the main gate,
wherein the second conductivity-type semiconductor layer has a region overlapping the source/drain regions, and
wherein the metal layer does not overlap the source/drain regions.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the first conductivity-type semiconductor layer of the main gate has a first thickness in a direction parallel to an upper surface of the substrate fully depleted by a gate voltage in a standby mode, and
the first conductivity-type semiconductor layer of the field pass gate has a second thickness in the direction parallel to the upper surface of the substrate greater than the first thickness.

### Claim 16

A semiconductor device, comprising:
a substrate including an active region and an element isolation region adjacent to the active region;
a first gate trench embedded in the active region;
a second gate trench embedded in the element isolation region,
wherein each of the first gate trench and the second gate trench includes a gate structure having a multilayer structure in which conductive materials having different work functions are sequentially stacked from corresponding lower portions of the first gate trench and the second gate trench, and
wherein each of the first gate trench and the second gate trench includes a lowermost first conductivity-type semiconductor layer having a first work function value, an uppermost second conductivity-type semiconductor layer having a second work function value, and a conductive layer between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer having a third work function value lower than the first work function value and higher than the second work function value.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the first conductivity-type semiconductor layer includes polycrystalline silicon doped with a p-type impurity, and the second conductivity-type semiconductor layer includes polycrystalline silicon doped with an n-type impurity.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the conductive layer includes a first portion having a first width which gradually decreases towards the lower portion of each of the first gate trench and the second gate trench and a second portion disposed on the first portion and having a second substantially uniform width wider than the first width in a direction parallel to an upper surface of the substrate.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein a thickness of the conductive layer of the gate structure of the second gate trench in a first direction perpendicular to an upper surface of the substrate is greater than a thickness of the conductive layer of the gate structure of the first gate trench in the first direction perpendicular to the upper surface of the substrate.