# US 10,319,725 B2 · Memory arrays

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- Number: US 10,319,725 B2
- Document ID: US10319725B2
- Status: Granted
- Kind: B2
- Application number: 15/391,719
- Filed: 2016-12-27
- Published: 2018-06-28
- Granted: 2019-06-11
- Earliest claimed: 2016-12-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Werner Juengling
- Web page: https://patentgrep.com/patent/US10319725B2

## CPC

- H10B 12/36: {the transistor being a FinFET}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/488: {Word lines}
- H10D 1/68: Capacitors having no potential barriers
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/834: {comprising FinFETs}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°. Wordline trunk regions extend across the array and along a third direction substantially orthogonal to the second direction of the columns. Wordline branch regions extend from the wordline trunk regions and along the first direction. Semiconductor-material fins are along the rows. Each semiconductor-material fin has a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. Each channel region is overlapped by a wordline branch. Digit lines extend along the columns and are electrically coupled with the second source/drain regions. Charge-storage devices are electrically coupled with the first source/drain regions.

## Claims

### Claim 1

A memory array, comprising:
memory cells arranged in rows and columns; the rows extending along a first direction and the columns extending along a second direction, with an angle between the first and second directions being less than 90°;
wordline trunk regions extending across the array and along a third direction substantially orthogonal to the second direction of the columns;
wordline branch regions extending from the wordline trunk regions and along the first direction;
semiconductor-material fins along the rows, each semiconductor-material fin having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions; each channel region being overlapped by a wordline branch region associated with the fin comprising the channel region; and
digit lines extending along the columns and being electrically coupled with the second source/drain regions.

### Claim 2 (depends on 1)

The memory array of claim 1 wherein each semiconductor-material fin has first and second sides in opposing relation to one another; wherein the wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another wordline branch region on the second side of the fin.

### Claim 3 (depends on 1)

The memory array of claim 1 wherein the wordline trunk regions are over conductive lines and are spaced from the conductive lines by dielectric material.

### Claim 4 (depends on 3)

The memory array of claim 3 wherein the wordline trunk regions comprise a same composition as the conductive lines.

### Claim 5 (depends on 3)

The memory array of claim 3 wherein the wordline trunk regions comprise a different composition than the conductive lines.

### Claim 6 (depends on 5)

The memory array of claim 5 wherein the wordline trunk regions comprise metal, and wherein the conductive lines consist of conductively-doped semiconductor material.

### Claim 7 (depends on 1)

The memory array of claim 1 further comprising charge-storage devices electrically coupled with the first source/drain regions.

### Claim 8

A memory array, comprising:
memory cells arranged in rows and columns; the rows extending along a first direction and the columns extending along a second direction, with an angle between the first and second directions being less than 90°;
semiconductor-material fins along the rows; each semiconductor-material fin having two first pedestals and a single second pedestal between the first pedestals; first source/drain regions being within the first pedestals, and a second source/drain region being within the second pedestal; a first channel region being between one of the first pedestals and the second pedestal, and a second channel region being between the other of the first pedestals and the second pedestal;
digit lines extending along the columns and being electrically coupled with the second source/drain regions; and
wordline branch regions extending along the first direction, and joining with wordline trunk regions that extend along a direction other than the first direction; the wordline branch regions extending along the semiconductor-material fins, each semiconductor-material fin having the first channel region overlapped by a first wordline branch region associated with the fin, and having the second channel region overlapped by a second wordline branch region associated with the fin; the first and second wordline branch regions along each semiconductor-material fin being spaced from one another by insulative structures that extend along the second pedestals of the semiconductor-material fins.

### Claim 9 (depends on 8)

The memory array of claim 8 wherein the wordline branch regions are taller in regions adjacent the wordline trunk regions and shorter in regions along the channel regions.

### Claim 10 (depends on 8)

The memory array of claim 8 wherein the wordline branch regions comprise a same composition as the wordline trunk regions.

### Claim 11 (depends on 8)

The memory array of claim 8 wherein the wordline trunk regions are over conductive lines.

### Claim 12 (depends on 11)

The memory array of claim 11 wherein the wordline branch regions are not over said conductive lines.

### Claim 13 (depends on 8)

The memory array of claim 8 further comprising charge-storage devices electrically coupled with the first source/drain regions.

### Claim 14 (depends on 13)

The memory array of claim 13 wherein the charge-storage devices are capacitors.

### Claim 15 (depends on 13)

The memory array of claim 13 wherein the charge-storage devices are ferroelectric capacitors.

### Claim 16 (depends on 8)

The memory array of claim 8 wherein each semiconductor-material fin has first and second sides in opposing relation to one another; wherein the first wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another first wordline branch region on the second side of the fin; and wherein the second wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another second wordline branch region on the second side of the fin.

### Claim 17

A memory array, comprising:
memory cells arranged in rows and columns; the rows extending along a first direction and the columns extending along a second direction, with an angle between the first and second directions being less than 90°;
semiconductor-material fins along the rows; each semiconductor-material fin having two first pedestals and a single second pedestal between the first pedestals; first source/drain regions being within the first pedestals, and a second source/drain region being within the second pedestal; a first channel region being between one of the first pedestals and the second pedestal, and a second channel region being between the other of the first pedestals and the second pedestal; the first source/drain region being beneath a first trough which is between said one of the first pedestals and the second pedestal, and the second source/drain region being beneath a second trough which is between said other of the first pedestals and the second pedestal;
digit lines extending along the columns and being electrically coupled with the second source/drain regions;
wordline trunk regions extending across the array and along a third direction substantially orthogonal to the second direction of the columns; and
wordline branch regions extending from the wordline trunk regions and along the first direction; the wordline branch regions extending along the semiconductor-material fins, each semiconductor-material fin having the first channel region overlapped by a first wordline branch region associated with the fin, and having the second channel region overlapped by a second wordline branch region associated with the fin and coupled with a different wordline trunk region than the first wordline branch region; the first wordline branch regions having tall regions along the wordline trunk regions and short regions extending under the first troughs, and the second wordline branch regions having tall regions along the wordline trunk regions and short regions extending under the second troughs.

### Claim 18 (depends on 17)

The memory array of claim 17 wherein each semiconductor-material fin has first and second sides in opposing relation to one another; wherein the first wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another first wordline branch region on the second side of the fin; and wherein the second wordline branch region associated with each fin is on the first side of the fin and is operationally paired with another second wordline branch region on the second side of the fin.

### Claim 19 (depends on 17)

The memory array of claim 17 wherein the wordline trunk regions are over conductive lines and are spaced from the conductive lines by dielectric material.

### Claim 20 (depends on 19)

The memory array of claim 19 wherein the wordline trunk regions comprise a same composition as the conductive lines.

### Claim 21 (depends on 19)

The memory array of claim 19 wherein the wordline trunk regions comprise a different composition than the conductive lines.

### Claim 22 (depends on 21)

The memory array of claim 21 wherein the wordline trunk regions comprise metal and the conductive lines consist of conductively-doped semiconductor material.

### Claim 23 (depends on 19)

The memory array of claim 19 wherein the wordline branch regions are not over the conductive lines.

### Claim 24 (depends on 17)

The memory array of claim 17 further comprising charge-storage devices electrically coupled with the first source/drain regions.