# US 10,319,724 B2 · Memory cells and memory arrays

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- Number: US 10,319,724 B2
- Document ID: US10319724B2
- Status: Granted
- Kind: B2
- Application number: 16/033,377
- Filed: 2018-07-12
- Published: 2018-11-15
- Granted: 2019-06-11
- Earliest claimed: 2016-08-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Suraj J. Mathew; Kris K. Brown; Raghunath Singanamalla; Vinay Nair; Fawad Ahmed; Fatma Arzum Simsek-Ege; Diem Thy N. Tran
- Web page: https://patentgrep.com/patent/US10319724B2

## CPC

- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/0383: {wherein the transistor is vertical}
- H10B 12/395: {the transistor being vertical}
- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10D 1/692: {Electrodes}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 89/10: Integrated device layouts
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10W 20/43: Layouts of interconnections
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

## Claims

### Claim 1

A memory cell comprising:
first, second and third transistors, with the third transistor being above the second transistor, and with the second and third transistors being above the first transistor; the first transistor having first and second source/drain regions, the second transistor having third and fourth source/drain regions, and the third transistor having fifth and sixth source/drain regions; wherein the memory cell includes a pillar of semiconductor material extending through the second and third transistors, and which includes the third, fourth, fifth and sixth source/drain regions as well as channel regions of the second and third transistors;
a write wordline which includes a gate of the first transistor;
a first bitline under the second transistor and electrically coupled with the first source/drain region;
a second bitline above the third transistor and electrically coupled with the sixth source/drain region;
a capacitor electrically coupled with the second source/drain region and electrically coupled with a gate of the second transistor;
wherein the capacitor is between a channel region of the second transistor and the gate of the second transistor; and
wherein the channel region of the second transistor is longer than a channel region of the third transistor.

### Claim 2

A memory cell, comprising:
first, second and third transistors, with the third transistor being above the second transistor, and with the second and third transistors being above the first transistor; the first transistor having first and second source/drain regions electrically coupled to one another through a first channel region, the second transistor having third and fourth source/drain regions electrically coupled to one another through a second channel region, the third transistor having fifth and sixth source/drain regions electrically coupled to one another through a third channel region; the fourth and fifth source/drain regions being electrically coupled to one another; the first, second and third transistors ascending upwardly relative to a semiconductor base in an order proceeding from the first transistor to the second transistor to the third transistor; the semiconductor base comprising monocrystalline semiconductor material;
a read bitline above the third transistor and electrically coupled with the sixth source/drain region;
a write bitline adjacent the first transistor and electrically coupled with the first source/drain region;
a write wordline which includes a gate of the first transistor;
a read wordline which includes a gate of the third transistor;
a capacitor electrically coupled with the second source/drain region and electrically coupled with a gate of the second transistor; and
wherein the capacitor is between a channel region of the second transistor and the gate of the second transistor.

### Claim 3

An apparatus comprising a semiconductor base and a plurality of memory cells, each of the plurality of memory cells comprising:
a first transistor including first and second source/drain regions formed in the semiconductor base, a first channel region therebetween and a first gate controlling the first channel region, the first gate being electrically connected to a first wordline;
a second transistor including third and fourth source/drain regions, a second channel region therebetween and a second gate controlling the second channel region, the third and fourth source/drain regions and the second channel region being vertically disposed with one another between a first bit line and a common plate over the semiconductor base, and the second gate being electrically coupled to the second source/drain region of the first transistor;
wherein each of the plurality of memory cells further comprises a third transistor disposed above the second transistor, the third transistor including fifth and sixth source/drain regions vertically disposed with one another and a third channel region therebetween, the fifth source/drain region electrically coupled with the fourth source/drain region; and
wherein the second channel region is larger than the third channel region in length.