# US 10,319,720 B2 · Integrated circuit device and method of manufacturing the same

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- Number: US 10,319,720 B2
- Document ID: US10319720B2
- Status: Granted
- Kind: B2
- Application number: 15/849,030
- Filed: 2017-12-20
- Published: 2019-01-10
- Granted: 2019-06-11
- Earliest claimed: 2017-07-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jung-hyuck Choi; Hae-wang Lee; Hyoun-jee Ha; Chul-hong Park
- Web page: https://patentgrep.com/patent/US10319720B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H03K 19/0944: using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence)
- H10D 30/0212: {using self-aligned silicidation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

## Claims

### Claim 1

An integrated circuit device comprising:
a plurality of fin-type active regions extending parallel to each other in a first direction on a substrate;
an insulating separation structure extending in a second direction that intersects the first direction on the plurality of fin-type active regions;
a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween, the pair of split gate lines extending in the second direction and aligned with the insulating separation structure;
a plurality of source/drain regions formed on the plurality of fin-type active regions; and
a jumper contact extending in the first direction between first and second source/drain regions of the plurality of source/drain regions, the first and second source/drain regions being spaced apart from each other with the insulating separation structure therebetween,
wherein the jumper contact passes over the insulating separation structure to connect the first and second source/drain regions to each other, and
wherein, in the second direction, the insulating separation structure is located between a first split gate line and a second split gate line of the pair of split gate lines.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, further comprising:
a first metal silicide film formed between the first source/drain region and the jumper contact; and
a second metal silicide film formed between the second source/drain region and the jumper contact.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1, further comprising:
a source/drain contact plug connected to a third source/drain region of the plurality of source/drain regions, the third source/drain region spaced apart from the first and second source/drain regions, the source/drain contact plug extending from the third source/drain region in a direction away from the substrate,
wherein a top surface of the jumper contact and a top surface of the source/drain contact plug are at the substantially same level, and
wherein a width of the top surface of the jumper contact is greater than a width of the top surface the source/drain contact plug in the first direction.

### Claim 4 (depends on 1)

The integrated circuit device of claim 1, wherein the substrate comprises a first device region where a first set of fin-type active regions of the plurality of fin-type active regions are arranged, a second device region where a second set of fin-type active regions of the plurality of fin-type active regions are arranged, and an inter-device separation region located between the first device region and the second device region,
wherein the first split gate line of the pair of split gate lines is located in the first device region and the inter-device separation region, and
wherein the second split gate line of the pair of split gate lines, the insulating separation structure, and the jumper contact are located in the second device region.

### Claim 5 (depends on 1)

The integrated circuit device of claim 1, wherein, in the second direction, a length between a first end and a second end of the jumper contact is less than a length between a first end and a second end of the insulating separation structure.

### Claim 6 (depends on 1)

The integrated circuit device of claim 1, wherein the insulating separation structure has a top surface having a rounded convex surface, and
wherein the jumper contact has a rounded concave surface contacting the rounded convex surface of the insulating separation structure and having a shape corresponding to a profile of the rounded convex surface.

### Claim 7 (depends on 1)

The integrated circuit device of claim 1, wherein, in the second direction, the first split gate line of the pair of split gate lines extends to a first end of the insulating separation structure and the second split gate line of the pair of split gate lines extends to a second end of the insulating separation structure.

### Claim 8 (depends on 1)

The integrated circuit device of claim 1, wherein the first and second source/drain regions are spaced apart from each other in the first direction.

### Claim 9 (depends on 1)

The integrated circuit device of claim 1, wherein a contact portion where a first end of the jumper contact contacts one of the first and second source/drain regions is located inside in the one of the first and second source/drain regions, in the first direction.

### Claim 10 (depends on 1)

The integrated circuit device of claim 1, wherein, the first split gate line, the insulating separation structure and the second split gate line extend linearly along a first geometric line.

### Claim 11

An integrated circuit device comprising:
a plurality of fin-type active regions extending parallel to each other in a first direction on a substrate;
an insulating separation structure extending in a second direction that intersects the first direction on the plurality of fin-type active regions;
a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween, the pair of split gate lines extending in the second direction and aligned with the insulating separation structure;
a plurality of source/drain regions formed on the plurality of fin-type active regions; and
a jumper contact extending in the first direction between first and second source/drain regions of the plurality of source/drain regions, the first and second source/drain regions being spaced apart from each other with the insulating separation structure therebetween,
wherein the jumper contact passes over the insulating separation structure to connect the first and second source/drain regions to each other, and
wherein the first and second source/drain regions are spaced apart from each other in the first direction.

### Claim 12 (depends on 11)

The integrated circuit device of claim 11, wherein the jumper contact comprises:
a pair of vertical extensions respectively connected to the first and second source/drain regions; and
a horizontal extension located over the insulating separation structure and extending in the first direction,
wherein the horizontal extension vertically overlaps the insulating separation structure and does not vertically overlap the pair of split gate lines.

### Claim 13 (depends on 11)

The integrated circuit device of claim 11, wherein a first fin-type active region of the fin-type active regions comprises a fin separation trench having a bottom surface at a level lower than a level of a top surface of the first fin-type active region, and
wherein the insulating separation structure comprises a buried separation portion filling the fin separation trench and a protruding separation portion integrally connected to the buried separation portion, extending away from the first fin-type active region, and protruding upward beyond the top surface of the first fin-type active region.

### Claim 14 (depends on 13)

The integrated circuit device of claim 13, wherein the insulating separation structure comprises a bottom surface contacting a top surface of the first fin-type active region and a top surface contacting the jumper contact.

### Claim 15 (depends on 11)

The integrated circuit device of claim 11, wherein a level of a lowermost surface of the insulating separation structure is lower or higher than a level of a bottom surface of each of the first and second source/drain regions.

### Claim 16 (depends on 11)

The integrated circuit device of claim 11, wherein the insulating separation structure comprises at least one of a single insulating film, a combination of a plurality of insulating films, and an air gap.

### Claim 17 (depends on 11)

The integrated circuit device of claim 11, wherein the pair of split gate lines includes a first split gate line and a second split gate line, and the first split gate line is a normal gate line and the second split gate line is a dummy gate line.