# US 10,319,717 B2 · Forming on-chip metal-insulator-semiconductor capacitor with pillars > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,717 B2 - Document ID: US10319717B2 - Status: Granted - Kind: B2 - Application number: 15/668,985 - Filed: 2017-08-04 - Published: 2018-05-03 - Granted: 2019-06-11 - Earliest claimed: 2016-10-31 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Zhenxing Bi; Kangguo Cheng; Peng Xu; Chen Zhang - Web page: https://patentgrep.com/patent/US10319717B2 ## CPC - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 1/711: {having non-planar surfaces, e.g. formed by texturisation} - H10D 1/716: {having vertical extensions} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 50/691: {for Group IV materials or Group III-V materials} - H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask} - H10P 50/71: {using masks for conductive or resistive materials} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure. The method further includes selectively removing the second polymer of the bi-polymer structure, doping the pillars, and depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate. ## Claims ### Claim 1 A method for forming a metal-insulator-semiconductor (MIS) capacitor over a semiconductor substrate, the method comprising: forming a plurality of fins; depositing a polymer between the plurality of fins; forming pillars by selectively removing the polymer and recessing the semiconductor substrate; depositing a dielectric between the pillars such that a top surface of the pillars is exposed; forming a first spacer over the pillars; and applying a first mask over the plurality of fins to etch the first spacer formed over the pillars. ### Claim 2 (depends on 1) The method of claim 1, wherein the plurality of fins are formed over a first region of the semiconductor substrate. ### Claim 3 (depends on 1) The method of claim 1, wherein the pillars are formed over a second region of the semiconductor structure. ### Claim 4 (depends on 1) The method of claim 1, wherein the polymer includes a bi-polymer structure. ### Claim 5 (depends on 4) The method of claim 4, further comprising depositing a directed self-assembly (DSA) co-polymer to form the bi-polymer structure by anneal. ### Claim 6 (depends on 1) The method of claim 1, wherein the pillars are doped after the first mask is applied over the plurality of fins. ### Claim 7 (depends on 6) The method of claim 6, wherein a high-k metal gate (HKMG) is deposited over the doped pillars to form the MIS capacitor. ### Claim 8 (depends on 7) The method of claim 7, wherein the first mask is stripped after doping the pillars and before depositing the HKMG over the doped pillars. ### Claim 9 (depends on 8) The method of claim 8, wherein a second mask is applied and a portion of the HKMG is etched to form a recess between the plurality of fins and the pillars. ### Claim 10 (depends on 9) The method of claim 9, wherein the second mask is stripped and the recess is filled with an oxide. ### Claim 11 (depends on 10) The method of claim 10, wherein the HKMG is recessed to expose a top portion of the plurality of fins. ### Claim 12 (depends on 11) The method of claim 11, wherein a second spacer is formed over exposed regions of the HKMG and between the plurality of fins. ### Claim 13 (depends on 12) The method of claim 12, wherein epitaxial growth is performed over the exposed top portions of the plurality of fins. ### Claim 14 A method for forming a metal-insulator-semiconductor (MIS) capacitor over a semiconductor substrate, the method comprising: forming a plurality of fins; depositing a polymer between the plurality of fins; forming pillars by selectively removing the polymer and recessing the semiconductor substrate; depositing a dielectric between the pillars such that a top surface of the pillars is exposed; forming a first spacer over the pillars and between the plurality of fins; applying a first mask over the plurality of fins; etching the first spacer formed over the pillars; etching the dielectric deposited between the pillars; and doping the pillars. ### Claim 15 (depends on 14) The method of claim 14, wherein the polymer includes a bi-polymer structure. ### Claim 16 (depends on 14) The method of claim 14, wherein a high-k metal gate (HKMG) is deposited over the doped pillars to form the MIS capacitor. ### Claim 17 (depends on 16) The method of claim 16, wherein the first mask is stripped after doping the pillars and before depositing the HKMG over the doped pillars. ### Claim 18 (depends on 17) The method of claim 17, wherein a second mask is applied and a portion of the HKMG is etched to form a recess between the plurality of fins and the pillars. ### Claim 19 (depends on 18) The method of claim 18, wherein the second mask is stripped, the recess is filled with an oxide, and the HKMG is recessed to expose a top portion of the plurality of fins. ### Claim 20 (depends on 19) The method of claim 19, wherein a second spacer is formed over exposed regions of the HKMG and between the plurality of fins; and wherein epitaxial growth is performed over the exposed top portions of the plurality of fins.