# US 10,319,715 B2 · Semiconductor devices including separate doped regions

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- Number: US 10,319,715 B2
- Document ID: US10319715B2
- Status: Granted
- Kind: B2
- Application number: 15/627,768
- Filed: 2017-06-20
- Published: 2018-06-14
- Granted: 2019-06-11
- Earliest claimed: 2016-12-09
- Assignees: Samsung Electroncis Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: YeonCheol Heo
- Web page: https://patentgrep.com/patent/US10319715B2

## CPC

- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 30/0318: {of vertical TFTs}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/133: {Emitter regions of BJTs}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device may include a substrate, a first doped region and a second doped region on the substrate, a base region on the first doped region, a channel region on the second doped region, and a third doped region and a fourth doped region on the base region and the channel region, respectively. The first doped region and the second doped region may be isolated from direct contact with each other in a first direction that is substantially parallel to a top surface of the substrate. A channel gate structure may be on a side surface of the channel region. A thickness of the base region, in a second direction that is substantially perpendicular to the top surface of the substrate, may be equal to or larger than a thickness of the channel region.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first doped region and a second doped region on the substrate, the first doped region and the second doped region isolated from direct contact with each other in a first direction, the first direction substantially parallel to a top surface of the substrate;
a base region on the first doped region;
a base contact region on the base region;
a channel region on the second doped region;
a third doped region and a fourth doped region on the base region and the channel region, respectively; and
a channel gate structure on a side surface of the channel region,
wherein the base contact region is isolated from direct contact with the third doped region in the first direction, and the base region and the base contact region are associated with a first conductivity type.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein,
the third doped region and the fourth doped region each have a substantially common magnitude of thickness in a second direction that is substantially perpendicular to the top surface of the substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein each doped region, of the first doped region and the second doped region, includes an edge portion and a center portion, the center portion protruding from the edge portion in a second direction that is substantially perpendicular to the top surface of the substrate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein the first doped region, the second doped region, the third doped region, and the fourth doped region are associated with a second conductivity type that is different from the first conductivity type.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein,
the channel gate structure encloses the channel region,
the channel gate structure includes a channel gate conductive layer and a channel gate insulating layer, and
the channel gate insulating layer is between the channel gate conductive layer and the channel region.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising:
a lower insulating layer on the first doped region and the second doped region,
wherein the lower insulating layer extends along a bottom surface of the channel gate structure and covers an interface between the second doped region and the channel region.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, further comprising:
a base gate structure extending along a side surface of the base region, the base gate structure enclosing the base region,
wherein the base gate structure includes a base gate conductive layer and a base gate insulating layer, and
wherein the base gate insulating layer is between the base gate conductive layer and the base region.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein,
the substrate includes a buried insulating layer, and
the first doped region and the second doped region are on the buried insulating layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein,
the substrate includes an impurity well,
the first doped region and the second doped region are on the impurity well,
the impurity well is associated with the first conductivity type, and
the first doped region and the second doped region are associated with a second conductivity type that is different from the first conductivity type.

### Claim 10

A semiconductor device, comprising:
a first doped region and a second doped region, the first doped region and the second doped region isolated from direct contact with each other in a first direction;
a base region and a channel region on the first doped region and the second doped region, respectively, in a second direction, the second direction being substantially perpendicular to the first direction; and
a third doped region and a fourth doped region on the base region and the channel region, respectively, in the second direction,
wherein each doped region, of the first doped region and the second doped region, includes an edge portion and a center portion, the edge portion of the first doped region extending in the first direction beyond a side surface of the base region and beyond a side surface of the third doped region such that the edge portion of the first doped region is exposed by both the base region and the third doped region, the edge portion of the second doped region extending in the first direction beyond a side surface of the channel region and beyond a side surface of the fourth doped region such that the edge portion of the second doped region is exposed by both the channel region and the fourth doped region, the center portion protruding from the edge portion in the second direction.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein,
the third doped region and the fourth doped region each have a substantially common magnitude of thickness in the second direction.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, further comprising:
a base contact region on the base region,
wherein the base contact region is isolated from direct contact with the third doped region in the first direction,
wherein the base region and the base contact region are associated with a first conductivity type, and
wherein the first doped region, the second doped region, the third doped region, and the fourth doped region are associated with a second conductivity type that is different from the first conductivity type.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, further comprising:
a lower insulating layer on the first doped region and the second doped region,
wherein the lower insulating layer covers an interface between the second doped region and the channel region.

### Claim 14

A semiconductor device, comprising:
a substrate, the substrate including a device isolation layer; and
a first semiconductor pattern and a second semiconductor pattern on the substrate, wherein
the first semiconductor pattern and the second semiconductor pattern are isolated from direct contact with each other in a first direction, such that the device isolation layer is between the first semiconductor pattern and the second semiconductor pattern in the first direction,
each given semiconductor pattern, of the first semiconductor pattern and the second semiconductor pattern, includes a lower doped region and an upper doped region in lower and upper portions of the given semiconductor pattern, respectively,
the first semiconductor pattern includes a base region between the upper doped region and the lower doped region of the first semiconductor pattern and a base contact region that is isolated from direct contact with the upper doped region of the first semiconductor pattern in the first direction, the base region and the base contact region are associated with a first conductivity type, and
the upper doped region and the lower doped region of each given semiconductor pattern are associated with a second conductivity type that is different from the first conductivity type.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein,
the first semiconductor pattern and the second semiconductor pattern each include a first doped region and a second doped region in an upper portion of the substrate, respectively, the first doped region and the second doped region being isolated from direct contact with each other in the first direction;
the first semiconductor pattern further includes a first semiconductor region on the first doped region, and a third doped region in an upper portion of the first semiconductor region, the third doped region vertically overlapped with the first doped region; and
the second semiconductor pattern further includes a second semiconductor region on the second doped region, and a fourth doped region in an upper portion of the second semiconductor region, the fourth doped region vertically overlapped with the second doped region.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further comprising:
a channel gate structure on a side surface of the second semiconductor pattern.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the channel gate structure includes,
a channel gate insulating layer on the side surface of the second semiconductor pattern, and
a channel gate conductive layer on the channel gate insulating layer.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, further comprising:
a base gate structure on a side surface of the base region.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein, the base gate structure includes,
a base gate insulating layer on the side surface of the base region, and
a base gate conductive layer on the base gate insulating layer.