# US 10,319,713 B2 · Semiconductor devices with electrostatic discharge robustness

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- Number: US 10,319,713 B2
- Document ID: US10319713B2
- Status: Granted
- Kind: B2
- Application number: 15/868,592
- Filed: 2018-01-11
- Published: 2018-07-26
- Granted: 2019-06-11
- Earliest claimed: 2017-01-20
- Assignees: Leadtrend Technology Corp.
- Applicants: Leadtrend Technology Corporation
- Inventors: Kuo-Chin Chiu; Chia-Wei Hung
- Web page: https://patentgrep.com/patent/US10319713B2

## CPC

- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 84/403: {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors}
- H10D 89/611: {using diodes as protective elements}
- H10D 89/811: {using FETs as protective elements}
- H10D 89/911: {using passive elements as protective elements}
- H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 10/60: Lateral BJTs
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/83: FETs having PN junction gate electrodes
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/111: {Field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)

## Abstract

An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.

## Claims

### Claim 1

A semiconductor device with electrostatic discharge robustness, comprising:
a semiconductor substrate of a first type;
a switch device, comprising:
a drain region formed on the semiconductor substrate, wherein the drain region is of a second type opposite to the first type;
a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction, wherein the first arch portion at least partially surrounds the drain region; and
a control gate, structured to control electric connection between the drain region and the source region; and
an ESD protection device, comprising:
a first region of the first type formed on the semiconductor substrate; and
a second region of the first type formed on the semiconductor substrate and with a second arch portion facing inwardly toward a second direction, wherein the second arch portion at least partially surrounds the first region;
wherein the first direction is opposite to the second direction, and the switch device is a depletion-mode junction effect transistor.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a first well region of the second type formed on the semiconductor substrate, wherein both the drain region and the first region are inside the first well region.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2, further comprising a drift region of the second type, wherein the drift region completely surrounds the first well region, and the source region is inside the drift region.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first region and the drain region are electrically connected to a pad.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the ESD protection device comprises a bipolar junction transistor where the first and second regions are emitter and collector of the bipolar junction transistor respectively.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the ESD protection device comprises a silicon controlled rectifier where the first and second regions are electrically connected to anode and cathode of the silicon controlled rectifier respectively.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the switch device comprises a third region of the first type, partially surrounding the source region and facing inwardly toward the first direction.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first direction and the second direction are aligned to each other.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the second region has two wall portions positioned at two opposite sides of the first region.

### Claim 10

A semiconductor device with electrostatic discharge robustness, comprising:
a switch device, comprising:
a drain region formed on a semiconductor substrate, wherein the semiconductor substrate is of a first type and the drain region is of a second type opposite to the first type; and
first doped strip regions, formed in a first racetrack pattern on the semiconductor substrate to partially surround the drain region; and
an ESD protection device formed on the semiconductor substrate, the ESD protection device comprising:
a central region of the first type, formed on the semiconductor substrate and adjoining the drain region; and
at least one second doped strip region, formed in a second racetrack pattern on the semiconductor substrate to partially surround the central region;
wherein the central region and the drain region are electrically connected to a pad, the switch device is a depletion-mode junction effect transistor, and one of the first doped strip regions acts as a source electrode of the depletion-mode junction effect transistor.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the first doped strip regions are formed to have a first arch portion facing inwardly toward a first direction, and the second doped strip region is formed to have a second arch portion facing inwardly toward a second direction opposite to the first direction.

### Claim 12 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the second doped strip region has two wall portions positioned at two opposite sides of the central region.

### Claim 13 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the ESD protection device comprises a silicon controlled rectifier where the central and the second doped strip region are anode and cathode of the silicon controlled rectifier respectively.

### Claim 14 (depends on 10)

The semiconductor device as claimed in claim 10, further comprises a drift region of the second type completely surrounding the central region and the drain region.