# US 10,319,709 B2 · Integrated circuits with standard cell

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- Number: US 10,319,709 B2
- Document ID: US10319709B2
- Status: Granted
- Kind: B2
- Application number: 15/987,911
- Filed: 2018-05-24
- Published: 2019-03-21
- Granted: 2019-06-11
- Earliest claimed: 2017-09-15
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chen-Hsien Hsu; Chien-Fu Chen; Cheng-Yang Tsai; Wei-Jen Wang; Chao-Wei Lin; Zhi-Hong Huang; Cheng-Tsung Ku; Chin-Sheng Yang
- Web page: https://patentgrep.com/patent/US10319709B2

## CPC

- H10D 89/10: Integrated device layouts
- H03K 19/0948: using CMOS {or complementary insulated gate field-effect transistors}
- H10D 84/853: {comprising FinFETs}
- H10D 84/907: {CMOS gate arrays}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H10D 62/834: further characterised by the dopants
- H10D 84/975: {Wiring regions or routing}
- H10D 86/215: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

## Claims

### Claim 1

An integrated circuit with a standard cell, comprising:
a first metal line and a second metal line, extending along a first direction;
a set of first dummy gates and a set of second dummy gates, extending along a second direction, wherein a region encompassed by the first metal line, the second metal line, the set of first dummy gates and the set of second dummy gates is defined as a standard cell region, and the standard cell region has an N-type region and a P-type region;
a plurality of fin structures disposed in the standard cell region, wherein the fin structures are parallel to the first direction;
two gate structures disposed in the standard cell region, being on the fin structures and parallel to the second direction;
three short contact plugs and three long contact plugs disposed in the standard cell region, wherein two of the long contact plugs are disposed between one of the gate structures and the set of first dummy gates, two of the short contact plugs are disposed between the two gate structures, and one of the long contact plugs and one of the short contact plugs are disposed between the other gate structure and the set of second dummy gates;
two gate contact plugs disposed on the two gate structures;
a plurality of via plugs disposed on and electrically connected to the long contact plugs, the short contact plugs and the gate contact plugs; and
a metal layer disposed on and electrically connected to the via plugs, wherein the metal layer comprises the first metal line, the second metal line, a third metal line, a fourth metal line and a fifth metal line.

### Claim 2 (depends on 1)

The integrated circuit according to claim 1, wherein the set of first dummy gates comprise two first dummy gates which do not contact each other, and the set of second dummy gates comprise two second dummy gates which do not contact each other.

### Claim 3 (depends on 1)

The integrated circuit according to claim 1, wherein an N number of fin structures are disposed in the P-type region and an M number of fin structures are disposed in the N-type region, N and M are odd numbers and N is greater than or equal to M.

### Claim 4 (depends on 1)

The integrated circuit according to claim 1, wherein projections along the first direction from the two long contact plugs between the gate structure and the set of first dummy gates completely coincide to each other.

### Claim 5 (depends on 1)

The integrated circuit according to claim 1, wherein projections along the first direction from the two short contact plugs between the two gate structures completely coincide to each other.

### Claim 6 (depends on 1)

The integrated circuit according to claim 1, wherein projections along the first direction from one of the long contact plugs and one of the short contact plugs between the gate structure and the set of second dummy gate completely coincide to each other.

### Claim 7 (depends on 1)

The integrated circuit according to claim 1, wherein the three long contact plugs further extend to outside of the standard cell region.

### Claim 8 (depends on 1)

The integrated circuit according to claim 1, wherein the via plugs comprise two short via plugs, three long via plugs and two gate via plugs.

### Claim 9 (depends on 8)

The integrated circuit according to claim 8, wherein the first metal line connects two of the long contact plugs, the second metal line connects the other one of the long contact plugs.

### Claim 10 (depends on 8)

The integrated circuit according to claim 8, wherein the third metal line connects one of the gate via plugs, the fourth metal line connects the other one of the gate via plugs, and the fifth metal line connects the two short via plugs.