# US 10,319,707 B2 · Semiconductor component, package structure and manufacturing method thereof

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- Number: US 10,319,707 B2
- Document ID: US10319707B2
- Status: Granted
- Kind: B2
- Application number: 15/717,920
- Filed: 2017-09-27
- Published: 2019-03-28
- Granted: 2019-06-11
- Earliest claimed: 2017-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ming-Fa Chen; Hsien-Wei Chen; Sung-Feng Yeh; Chi-Hwang Tai
- Web page: https://patentgrep.com/patent/US10319707B2

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10W 46/301: {for alignment}
- H10W 70/655: Fan-out layouts
- H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The at least one semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the at least one semiconductor device and adheres the at least one semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the at least one semiconductor device, wherein the at least one semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the at least one semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure.

## Claims

### Claim 1

A method for manufacturing a package structure, comprising:
providing a semiconductor substrate;
forming a first bonding layer on the semiconductor substrate;
disposing at least one semiconductor device on the semiconductor substrate;
fusion bonding the at least one semiconductor device to the semiconductor substrate through a portion of the first bonding layer;
forming an insulating encapsulation to at least wrap a sidewall of the at least one semiconductor device;
performing a first planarizing step to planarize the insulating encapsulation;
forming a redistribution circuit structure on the at least one semiconductor device and on the insulating encapsulation; and
disposing conductive elements on the redistribution circuit structure.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the first bonding layer is formed in a blanket manner to cover on the semiconductor substrate.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein forming the insulating encapsulation comprises performing a chemical vapor deposition process.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein after performing the first planarizing step and prior to forming the redistribution circuit structure on the at least one semiconductor device and on the insulating encapsulation, the method further comprises:
forming at least one conductive pillar embedded in the at least one semiconductor device and having a surface exposed by a surface of the at least one semiconductor device, wherein the redistribution circuit structure is electrically connected to the at least one semiconductor device through the at least one conductive pillar.

### Claim 5 (depends on 1)

The method as claimed in claim 1, further comprising:
forming connecting pads between the conductive elements on the redistribution circuit structure, wherein the conductive elements are connected to the redistribution circuit structure through the connecting pads, and the redistribution circuit structure is located between the at least one semiconductor device and the conductive elements and between the at least one semiconductor device and the connecting pads.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein prior to disposing the at least one semiconductor device on the semiconductor substrate, the method further comprises:
forming a semiconductor component having the at least one semiconductor device, wherein forming the semiconductor component having the at least one semiconductor device comprises:
providing a first semiconductor carrier;
forming a second bonding layer on the first semiconductor carrier;
disposing a second semiconductor carrier on the first semiconductor carrier;
fusion bonding the second semiconductor carrier to the first semiconductor carrier through the second bonding layer;
performing a second planarizing step on the first semiconductor carrier;
performing a third planarizing step on the second semiconductor carrier; and
performing a dicing process.

### Claim 7 (depends on 6)

The method as claimed in claim 6, wherein after disposing at least one semiconductor device on the semiconductor substrate and prior to forming the insulating encapsulation, the method further comprising:
performing a fourth planarizing step on the second semiconductor carrier of the semiconductor component having the at least one semiconductor device.

### Claim 8 (depends on 7)

The method as claimed in claim 7, wherein performing the first planarizing step to planarize the insulating encapsulation further comprises:
removing the second semiconductor carrier and the second bonding layer of the semiconductor component having the at least one semiconductor device.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein after performing the first planarizing step and prior to forming the redistribution circuit structure on the at least one semiconductor device and on the insulating encapsulation, the method further comprises:
forming at least one conductive pillar embedded in the at least one semiconductor device comprised in the semiconductor component and having a surface exposed by a surface of the at least one semiconductor device comprised in the semiconductor component, wherein the redistribution circuit structure is electrically connected to the at least one semiconductor device comprised in the semiconductor component through the at least one conductive pillar.

### Claim 10 (depends on 6)

The method as claimed in claim 6, wherein the second bonding layer is formed in a blanket manner to cover on the first semiconductor carrier.

### Claim 11

A method for manufacturing a semiconductor component, comprising:
providing a first semiconductor carrier;
forming a bonding layer on the first semiconductor carrier;
disposing a second semiconductor carrier on the first semiconductor carrier;
fusion bonding the second semiconductor carrier to the first semiconductor carrier through the bonding layer, the second semiconductor carrier being bonded on a surface of the bonding layer, and an entire continuous surface of the second semiconductor carrier being in physical contact with the surface of the bonding layer;
performing a first planarizing step on the first semiconductor carrier;
performing a second planarizing step on the second semiconductor carrier; and
performing a dicing process.

### Claim 12 (depends on 11)

The method as claimed in claim 11, wherein the bonding layer is formed in a blanket manner to cover on the first semiconductor carrier.

### Claim 13

A method for manufacturing a package structure, comprising:
providing a semiconductor substrate;
forming a first bonding layer on the semiconductor substrate;
disposing a semiconductor device on the semiconductor substrate;
fusion bonding the semiconductor device to the semiconductor substrate through the first bonding layer;
encapsulating the semiconductor device by an insulating encapsulation; and
forming a redistribution circuit structure on the semiconductor device and on the insulating encapsulation.

### Claim 14 (depends on 13)

The method as claimed in claim 13, wherein the first bonding layer is formed in a blanket manner to cover on the semiconductor substrate.

### Claim 15 (depends on 13)

The method as claimed in claim 13, wherein encapsulating the semiconductor device by the insulating encapsulation comprises performing a chemical vapor deposition process to form the insulating encapsulation.

### Claim 16 (depends on 13)

The method as claimed in claim 13, wherein after encapsulating the semiconductor device by the insulating encapsulation and prior to forming the redistribution circuit structure on the semiconductor device and on the insulating encapsulation, the method further comprises:
performing a first planarizing step to planarize the insulating encapsulation; and
forming at least one conductive pillar embedded in the semiconductor device and having a surface exposed by a surface of the semiconductor device, wherein the redistribution circuit structure is electrically connected to the semiconductor device through the at least one conductive pillar.

### Claim 17 (depends on 13)

The method as claimed in claim 13, further comprising:
forming conductive elements on the redistribution circuit structure, wherein the conductive elements are connected to the redistribution circuit structure, and the redistribution circuit structure is located between the semiconductor device and the conductive elements.

### Claim 18 (depends on 13)

The method as claimed in claim 13, wherein prior to disposing the semiconductor device on the semiconductor substrate, the method further comprises:
forming a semiconductor component having the semiconductor device, wherein forming the semiconductor component having the semiconductor device comprises:
providing a first semiconductor carrier;
forming a second bonding layer on the first semiconductor carrier;
disposing a second semiconductor carrier on the first semiconductor carrier;
fusion bonding the second semiconductor carrier to the first semiconductor carrier through the second bonding layer;
performing a second planarizing step on the first semiconductor carrier;
performing a third planarizing step on the second semiconductor carrier; and
performing a dicing process.

### Claim 19 (depends on 18)

The method as claimed in claim 18, wherein after disposing semiconductor device on the semiconductor substrate and prior to encapsulating the semiconductor device by the insulating encapsulation, the method further comprising:
performing a fourth planarizing step on the second semiconductor carrier of the semiconductor component having the semiconductor device.

### Claim 20 (depends on 19)

The method as claimed in claim 19, wherein after encapsulating the semiconductor device by the insulating encapsulation and prior to forming the redistribution circuit structure on the semiconductor device and on the insulating encapsulation further comprises:
removing the second semiconductor carrier and the second bonding layer of the semiconductor component having the semiconductor device.

### Claim 21 (depends on 20)

The method as claimed in claim 20, wherein after removing the second semiconductor carrier and the second bonding layer of the semiconductor component having the semiconductor device and prior to forming the redistribution circuit structure on the semiconductor device and on the insulating encapsulation, the method further comprises:
forming at least one conductive pillar embedded in the semiconductor device comprised in the semiconductor component and having a surface exposed by a surface of the semiconductor device comprised in the semiconductor component, wherein the redistribution circuit structure is electrically connected to the semiconductor device comprised in the semiconductor component through the at least one conductive pillar.

### Claim 22 (depends on 18)

The method as claimed in claim 18, wherein the second bonding layer is formed in a blanket manner to cover on the first semiconductor carrier.