# US 10,319,704 B2 · Semiconductor module

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- Number: US 10,319,704 B2
- Document ID: US10319704B2
- Status: Granted
- Kind: B2
- Application number: 15/739,424
- Filed: 2016-01-31
- Published: 2018-06-28
- Granted: 2019-06-11
- Earliest claimed: 2016-01-31
- Assignees: Shindengen Electric Manufacturing Co., Ltd.
- Applicants: Shindengen Electric Manufacturing Co., Ltd.
- Inventors: Kosuke Ikeda; Yuji Morinaga
- Web page: https://patentgrep.com/patent/US10319704B2

## CPC

- H10W 90/00: Package configurations
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 40/778: {in encapsulations}
- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 70/635: {Through-vias}
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/10: characterised by their shape or disposition
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/40: characterised by their materials
- H10W 76/15: Containers comprising an insulating or insulated base
- H10W 76/47: Solid or gel fillings
- H10W 76/60: Seals
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07354: {changes in dispositions}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/381: {Auxiliary members}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/646: {the connected ends being on auxiliary connecting means on bond pads, e.g. on a bump connector}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/871: {Bond wires and strap connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/886: {Die-attach connectors and strap connectors}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 76/138: having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type
- H10W 90/20: Configurations of stacked chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/764: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor module includes: a first substrate having a first insulating substrate and a first conductor layer; a power device part having a first electrode, a second electrode and a gate electrode; a second substrate having a second insulating substrate and a second conductor layer, wherein the second conductor layer has a bonding portion and a surrounding wall portion formed at a position which surrounds the bonding portion as viewed in a plan view; an inner resin portion; a control IC; and an outer resin portion, wherein the power device part is disposed such that the gate electrode is positioned outside a region defined by the surrounding wall portion as viewed in a plan view, and the gate electrode is electrically connected to an output terminal of the control IC through a connecting member.

## Claims

### Claim 1

A semiconductor module comprising:
a first substrate having a first insulating substrate and a first conductor layer which is formed on at least one surface of the first insulating substrate;
a power device part having a first electrode on one surface thereof and a second electrode and a gate electrode on the other surface thereof and having the first electrode bonded to the first conductor layer;
a second substrate having a second insulating substrate and a second conductor layer formed on at least one surface of the second insulating substrate, wherein the second conductor layer has a bonding portion bonded to the second electrode and a surrounding wall portion formed at a position which surrounds the bonding portion as viewed in a plan view in a state where an upper end surface of the surrounding wall portion projects from a bonding surface between the bonding portion and the second electrode, and the second substrate is in contact with the first substrate by way of the surrounding wall portion;
an inner resin portion made of a resin and disposed in a space defined by the surrounding wall portion and sandwiched between the first insulating substrate and the second insulating substrate;
a control IC disposed at a position being spaced apart from the power device part; and
an outer resin portion made of a resin and disposed on one surface side of the first substrate so as to cover at least the second substrate and the control IC, wherein
the power device part is disposed such that the gate electrode is positioned outside a region defined by the surrounding wall portion as viewed in a plan view, and
the gate electrode is electrically connected to an output terminal of the control IC through a predetermined connecting member.

### Claim 2 (depends on 1)

The semiconductor module according to claim 1, wherein the surrounding wall portion is formed only at a predetermined portion of a position which surrounds the bonding portion as viewed in a plan view.

### Claim 3 (depends on 1)

The semiconductor module according to claim 1, wherein the power device part is formed of one semiconductor element, and
the semiconductor element has a first electrode on one surface thereof and has a second electrode and a gate electrode on the other surface thereof.

### Claim 4 (depends on 1)

The semiconductor module according to claim 1, wherein the power device part has the structure where a plurality of semiconductor elements are stacked,
both of at least two semiconductor elements among the plurality of semiconductor elements have a first electrode on one surface thereof and have a second electrode and a gate electrode on the other surface thereof, and
the at least two semiconductor elements are stacked such that the at least two semiconductor elements are positioned at a position where the gate electrodes of the at least two respective semiconductor elements do not overlap with each other as viewed in a plan view.

### Claim 5 (depends on 1)

The semiconductor module according to claim 1, wherein the power device part has the structure where a plurality of semiconductor elements are stacked, and
at least one semiconductor element among the plurality of semiconductor elements has a first electrode on one surface thereof and has a second electrode and a gate electrode on the other surface thereof.

### Claim 6 (depends on 1)

The semiconductor module according to claim 1, wherein the surrounding wall portion is formed continuously with the bonding portion,
the first substrate further has a third conductor layer which is bonded to the surrounding wall portion at a position spaced apart from the first conductor layer on one surface of the first insulating substrate, and
the third conductor layer is electrically connected to the second electrode through the surrounding wall portion and the bonding portion.

### Claim 7 (depends on 6)

The semiconductor module according to claim 6, wherein a groove portion which engages with the surrounding wall portion is formed on the third conductor layer.

### Claim 8 (depends on 1)

The semiconductor module according to claim 1, wherein the surrounding wall portion is formed in a state where the surrounding wall portion is spaced apart from the bonding portion.

### Claim 9 (depends on 8)

The semiconductor module according to claim 8, wherein the first substrate further has a third conductor layer which is bonded to the surrounding wall portion at a position spaced apart from the first conductor layer on one surface of the first insulating substrate, and
a groove portion which engages with the surrounding wall portion is formed on the third conductor layer.

### Claim 10 (depends on 1)

The semiconductor module according to claim 1, wherein a power-device-part mounting conductor layer is formed on the other surface of the second substrate, and
a second power device part is disposed on the power-device-part mounting conductor layer.

### Claim 11 (depends on 10)

The semiconductor module according to claim 10, wherein the second power device part has a first electrode which is electrically connected to the power-device-part mounting conductor layer on one surface thereof,
a hole is formed in the second insulating substrate at a position corresponding to the bonding portion,
a second connecting member is disposed in the inside of a hole formed in the second insulating substrate; and
the first electrode of the second power device part is electrically connected to the second electrode of the power device part through the second connecting member.

### Claim 12 (depends on 1)

The semiconductor module according to claim 1, wherein the bonding portion and the surrounding wall portion are formed of one copper layer.