# US 10,319,702 B2 · Semiconductor packages

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- Number: US 10,319,702 B2
- Document ID: US10319702B2
- Status: Granted
- Kind: B2
- Application number: 15/860,730
- Filed: 2018-01-03
- Published: 2019-02-14
- Granted: 2019-06-11
- Earliest claimed: 2017-08-09
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Chul Park; Seonggwan Lee; Minkyeong Park
- Inventors: Chul Park; Seonggwan Lee; Minkyeong Park
- Web page: https://patentgrep.com/patent/US10319702B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/07354: {changes in dispositions}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/381: {Auxiliary members}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/90: Bond pads, in general
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.

## Claims

### Claim 1

A semiconductor package comprising:
a substrate comprising a signal pattern on an upper surface thereof;
a chip stack on the upper surface of the substrate; and
a first semiconductor chip and one or more spacers that are between the substrate and the chip stack,
wherein the first semiconductor chip and the one or more spacers are spaced apart from each other,
wherein the chip stack comprises one or more second semiconductor chips stacked on the substrate, and a third semiconductor chip between the substrate and the chip stack,
wherein the one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view, and
wherein the one or more spacers have a same planar shape as the first semiconductor chip,
wherein the third semiconductor chip is laterally spaced apart from the first semiconductor chip and the one or more spacers and is opposite to the first semiconductor chip,
wherein the chip stack further comprises one or more fourth semiconductor chips on the one or more second semiconductor chips,
wherein the one or more second semiconductor chips have a first offset stack structure of a first stepped shape tilted in a first direction, and
wherein the one or more fourth semiconductor chips have a second offset stack structure of a second stepped shape tilted in a second direction that is opposite the first direction,
wherein the signal pattern comprises a third signal pad spaced apart from the chip stack in the first direction and electrically connected to the third semiconductor chip, and a fourth signal pad spaced apart from the chip stack in the first direction and electrically connected to at least one of the fourth semiconductor chips, and
wherein a third distance between the third signal pad and the fourth signal pad is less than a fourth distance between the fourth signal pad and a second side of the lowermost second semiconductor chip.

### Claim 2 (depends on 1)

The semiconductor package according to claim 1, wherein a gap between the one or more spacers and the first semiconductor chip comprises a first line region extending in a first direction and a second line region extending in a second direction perpendicular to the first direction.

### Claim 3 (depends on 2)

The semiconductor package according to claim 2, further comprising:
a molding layer covering the chip stack and filling the gap.

### Claim 4 (depends on 1)

The semiconductor package according to claim 1,
wherein the lowermost second semiconductor chip has a first side and a second side that are opposite to each other in a first direction, and
wherein a side of the first semiconductor chip is aligned with the first side of the lowermost second semiconductor chip.

### Claim 5 (depends on 1)

The semiconductor package according to claim 1, wherein the first semiconductor chip and the one or more spacers that have the same planar shape as the first semiconductor chip are respectively adjacent to opposite ones of the corners of the lowermost second semiconductor chip, in plan view.

### Claim 6 (depends on 1)

The semiconductor package according to claim 1,
wherein the lowermost second semiconductor chip has a first side and a second side that are opposite to each other in a first direction, and
wherein the chip stack has an offset stack structure in a stepped shape tilted in a second direction that is opposite to the first direction.

### Claim 7 (depends on 6)

The semiconductor package according to claim 6, wherein the signal pattern comprises:
a first signal pad spaced apart from the chip stack in the second direction and electrically connected to the first semiconductor chip,
a second signal pad spaced apart from the chip stack in the second direction and electrically connected to the one or more second semiconductor chips; and
a conductive line connecting the first signal pad and the second signal pad.

### Claim 8 (depends on 7)

The semiconductor package according to claim 7, wherein a first distance between the first signal pad and the second signal pad is less than a second distance between the second signal pad and the first side of the lowermost second semiconductor chip.

### Claim 9 (depends on 1)

The semiconductor package according to claim 1,
wherein the chip stack has a vertical stack structure in which the one or more second semiconductor chips substantially overlap each other entirely, and
wherein the one or more second semiconductor chips are electrically connected to the first semiconductor chip through a through-silicon-via passing through the chip stack.

### Claim 10 (depends on 1)

The semiconductor package according to claim 1,
wherein a side of the third semiconductor chip is aligned with a side of the lowermost second semiconductor chip.

### Claim 11 (depends on 1)

The semiconductor package according to claim 1,
wherein at least one of the one or more second semiconductor chips of the chip stack does not overlap the first semiconductor chip in the plan view.