# US 10,319,700 B1 · Stacked semiconductor architecture including semiconductor dies and thermal spreaders on a base die

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- Number: US 10,319,700 B1
- Document ID: US10319700B1
- Status: Granted
- Kind: B1
- Application number: 15/859,404
- Filed: 2017-12-30
- Published: 2019-07-04
- Granted: 2019-06-11
- Earliest claimed: 2017-12-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Edward A. Burton
- Web page: https://patentgrep.com/patent/US10319700B1

## CPC

- H10W 90/00: Package configurations
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/251: {Organics}
- H10W 40/253: {Semiconductors}
- H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 40/77: Auxiliary members characterised by their shape
- H10W 72/013: {of die-attach connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/265: {Providing thermal transfer, e.g. thermal bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 90/20: Configurations of stacked chips
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.

## Claims

### Claim 1

A stacked semiconductor architecture for a semiconductor package, comprising:
a base die;
a plurality of stacked semiconductor dies on the base die;
a plurality of thermal spreaders on the base die, the plurality of thermal spreaders disposed on the base die in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies; and
a heat sink disposed on exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders, wherein the heat sink is electrically coupled to the base die.

### Claim 2 (depends on 1)

The stacked semiconductor architecture of claim 1, further comprising electrical connections between two or more of the base die, the plurality of stacked semiconductor dies, and the plurality of thermal spreaders.

### Claim 3 (depends on 1)

The stacked semiconductor architecture of claim 1, further comprising a heat sink disposed on exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

### Claim 4 (depends on 3)

The stacked semiconductor architecture of claim 3, wherein a thermal interface material (TIM) layer is disposed between: (i) the heat sink; and (ii) the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

### Claim 5 (depends on 1)

The stacked semiconductor architecture of claim 1, wherein at least one of the thermal spreaders is formed from a metal or a metal alloy.

### Claim 6 (depends on 1)

The stacked semiconductor architecture of claim 1, wherein at least one of the thermal spreaders includes a silicon semiconductor die.

### Claim 7 (depends on 1)

The stacked semiconductor architecture of claim 1, wherein at least one of the thermal spreaders is formed from a silicon semiconductor die with one or more metal layers formed thereon.

### Claim 8

A stacked semiconductor architecture for a semiconductor package, comprising:
a base die;
a plurality of stacked semiconductor dies on the base die; and
a plurality of thermal spreaders on the base die, the plurality of thermal spreaders disposed on the base die in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies, wherein at least one of the thermal spreaders is formed from a plurality of interleaved dielectric and metal layers.

### Claim 9

A method of forming a stacked semiconductor architecture for a semiconductor package, comprising:
disposing a plurality of stacked semiconductor dies on a base die;
disposing a plurality of thermal spreaders on the base die, the plurality of thermal spreaders arranged on the base die in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies; and
electrically coupling the base die to the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
applying a thermal interface material (TIM) layer on the base die in the one or more gaps or in the one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies prior to disposing the plurality of thermal spreaders on the base die.

### Claim 11 (depends on 9)

The method of claim 9, further comprising:
applying a thermal interface material (TIM) layer on exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
disposing a heat sink on the exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
electrically coupling the heat sink to the base die.

### Claim 14 (depends on 9)

The method of claim 9, wherein at least one of the thermal spreaders is formed from a metal or a metal alloy.

### Claim 15 (depends on 9)

The method of claim 9, wherein at least one of the thermal spreaders includes a silicon semiconductor die.

### Claim 16 (depends on 9)

The method of claim 9, wherein at least one of the thermal spreaders is formed from a silicon semiconductor die with one or more metal layers formed thereon.

### Claim 17 (depends on 9)

The method of claim 9, wherein at least one of the thermal spreaders is formed from a plurality of interleaved dielectric and metal layers.

### Claim 18

A semiconductor package, comprising:
a base die;
a plurality of stacked semiconductor dies on the base die;
a plurality of thermal spreaders on the base die, the plurality of thermal spreaders disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies; and
electrical connections between two or more of the base die, the plurality of stacked semiconductor dies, and the plurality of thermal spreaders.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, further comprising a heat sink disposed on exposed surfaces of the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

### Claim 20 (depends on 19)

The semiconductor package of claim 19, wherein a thermal interface material (TIM) layer is disposed between: (i) the heat sink; and (ii) the plurality of stacked semiconductor dies and the plurality of thermal spreaders.

### Claim 21 (depends on 19)

The semiconductor package of claim 19, wherein the heat sink is electrically coupled to the base die.

### Claim 22 (depends on 18)

The semiconductor package of claim 18, wherein at least one of the thermal spreaders is formed from a metal or a metal alloy.

### Claim 23 (depends on 18)

The semiconductor package of claim 18, wherein at least one of the thermal spreaders includes a silicon semiconductor die.

### Claim 24 (depends on 18)

The semiconductor package of claim 18, wherein at least one of the thermal spreaders is formed from a silicon semiconductor die with one or more metal layers formed thereon.

### Claim 25 (depends on 18)

The semiconductor package of claim 18, wherein at least one of the thermal spreaders is formed from a plurality of interleaved dielectric and metal layers.