# US 10,319,698 B2 · Microelectronic device package having alternately stacked die

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- Number: US 10,319,698 B2
- Document ID: US10319698B2
- Status: Granted
- Kind: B2
- Application number: 15/354,291
- Filed: 2016-11-17
- Published: 2018-05-17
- Granted: 2019-06-11
- Earliest claimed: 2016-11-17
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Bok Eng Cheah; Min Suet Lim; Jackson Chung Peng Kong
- Web page: https://patentgrep.com/patent/US10319698B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 74/124: {the encapsulations having cavities other than that occupied by chips}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/07354: {changes in dispositions}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/327: {Multiple die-attach connectors having different sizes}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic device package including multiple layers of stacked die. Multiple die layers in the package can include two or more die. At least two die in a first layer will be laterally spaced from one another to define a first gap extending in a first direction; and at least two die in a second layer will be laterally spaced from one another to define a second gap extending in a second direction that is angularly offset from the first direction. The first and second directions can be perpendicular to one another.

## Claims

### Claim 1

A microelectronic device, comprising:
a substrate;
first and second semiconductor die supported by the substrate in laterally spaced relation to one another defining a first gap extending in a first direction;
third and fourth semiconductor die extending over the first and second semiconductor die and in laterally spaced relation to one another defining a second gap extending in a second direction angularly offset from the first direction of the first gap; and
fifth and sixth semiconductor die extending over the third and fourth semiconductor die and in laterally spaced relation to one another defining a third gap extending in a third direction angularly offset from the second direction, wherein the third direction and the first direction are the same.

### Claim 2 (depends on 1)

The microelectronic device of claim 1, wherein the second gap extends perpendicular to the first gap.

### Claim 3 (depends on 1)

The microelectronic device of claim 1, wherein the first and second semiconductor die are directly connected to the substrate.

### Claim 4 (depends on 1)

The microelectronic device of claim 1, wherein the third and fourth semiconductor die each extend across and is connected to each of said first and second die.

### Claim 5 (depends on 1)

The microelectronic device of claim 1, wherein one of the first and second gaps extends vertically adjacent a thermally active region of at least one die.

### Claim 6 (depends on 1)

The microelectronic device of claim 1, wherein at least one die includes multiple vertical interconnects electrically coupling respective contacts of another die above such die, to contacts extending below such die.

### Claim 7 (depends on 6)

The microelectronic device of claim 6, wherein the multiple vertical interconnects comprise multiple through-silicon vias.

### Claim 8 (depends on 1)

The microelectronic device of claim 1, wherein the substrate is a package substrate.

### Claim 9

A microelectronic device, comprising
a substrate; and
multiple layers of semiconductor die supported by the substrate, the multiple layers including,
first and second layers that each include at least two die in spaced relation to one another to define a respective gap between the die, and
a third layer of semiconductor die above the second layer of the multiple layers, the third layer of semiconductor die including at least two die in spaced relation to one another to define a gap between such die; and
wherein the gap between die in the first layer extends in a first direction, wherein the gap between die in the second layer extends in a second direction angularly offset from the first direction, and wherein the gap between the at least two die in the third layer extends in the first direction.

### Claim 10 (depends on 9)

The microelectronic device of claim 9, wherein at least one layer of the multiple layers comprises at least first, second, and third die arranged to define two gaps between laterally adjacent die, the two gaps extending in parallel to one another.

### Claim 11

An electronic system, comprising:
a microelectronic device, comprising,
a substrate,
a first semiconductor die layer including first and second semiconductor die supported by the substrate in laterally spaced relation to one another defining a first gap extending in a first direction,
a second semiconductor die layer including third and fourth semiconductor die extending over the first and second semiconductor die and in laterally spaced relation to one another defining a second gap extending in a second direction perpendicular to the first direction of the first gap;
a third semiconductor die layer including fifth and sixth semiconductor die extending over the third and fourth semiconductor die and in laterally spaced relation to one another defining a third gap extending in the first direction; and
at least one of a mass storage device and a network interface operably coupled to the microelectronic device.

### Claim 12 (depends on 11)

The electronic system of claim 11, wherein the first and second semiconductor die are coupled directly to the substrate.

### Claim 13 (depends on 11)

The electronic system of claim 11, wherein one of the defined gaps in one of the layers extends adjacent a thermally active region of at least one die in a vertically adjacent layer.

### Claim 14 (depends on 9)

The microelectronic device of claim 9, wherein at least one die includes multiple vertical interconnects electrically coupling respective contacts of another die above such die, to contacts extending below such die.

### Claim 15 (depends on 11)

The electronic system of claim 11, wherein the microelectronic device includes at least one die including multiple vertical interconnects electrically coupling respective contacts of another die above such die, to contacts extending below such die.