# US 10,319,695 B2 · Semiconductor device and bump formation process

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,695 B2
- Document ID: US10319695B2
- Status: Granted
- Kind: B2
- Application number: 15/715,659
- Filed: 2017-09-26
- Published: 2019-01-03
- Granted: 2019-06-11
- Earliest claimed: 2017-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Sheng-Yu Wu; Ching-Hui Chen; Mirng-Ji Lii; Kai-Di Wu; Chien-Hung Kuo; Chao-Yi Wang; Hon-Lin Huang; Zi-Zhong Wang; Chun-Mao Chiu
- Web page: https://patentgrep.com/patent/US10319695B2

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising:
forming a first sacrificial layer over a semiconductor substrate;
forming a first opening in the first sacrificial layer to expose a conductive pad over the semiconductor substrate;
forming a conductive bump in the first opening;
forming a barrier layer on sidewalls of the first opening, on a top surface of the first sacrificial layer, and on a top surface of the conductive bump;
removing a portion of the barrier layer from the top surface of the first sacrificial layer;
forming a conductive cap in the first opening with the barrier layer interposing in between the conductive bump and the conductive cap; and
removing the first sacrificial layer.

### Claim 2 (depends on 1)

The method of fabricating the semiconductor device of claim 1, wherein the portion of the barrier layer on the top surface of the first sacrificial layer is removed by chemical mechanical planarization.

### Claim 3 (depends on 1)

The method of fabricating the semiconductor device of claim 1, further comprising:
forming a second sacrificial layer over the first sacrificial layer after the
forming the conductive cap in the first opening;
forming a second opening in the second sacrificial layer exposing a top surface of the conductive cap;
forming an adhesion film on the second sacrificial layer and in the second opening; and
removing the second sacrificial layer.

### Claim 4 (depends on 1)

The method of fabricating the semiconductor device of claim 1, wherein the barrier layer comprises titanium, cobalt, or combinations thereof.

### Claim 5

A method of fabricating a semiconductor device, the method comprising:
forming a conductive pad above a substrate;
forming a passivation layer above the conductive pad;
forming a sacrificial layer above the passivation layer;
forming an opening in the passivation layer and the sacrificial layer, above the conductive pad, and that exposes the conductive pad, wherein forming the opening includes forming a first recess and a second recess that is above the first recess and that has a larger width than the first recess;
forming a micro bump in the opening; and
removing the sacrificial layer from a sidewall of the micro bump.

### Claim 6 (depends on 5)

The method of claim 5, further comprising forming the second recess that extends from a top surface of the sacrificial layer to a position above a bottom surface of the sacrificial layer.

### Claim 7 (depends on 5)

The method of claim 5, further comprising forming the first recess that extends from a position between a top surface and a bottom surface of the sacrificial layer to a bottom surface of the passivation layer.

### Claim 8 (depends on 5)

The method of claim 5, further comprising forming the second recess that extends from a top surface of the sacrificial layer to a bottom surface of the sacrificial layer.

### Claim 9 (depends on 5)

The method of claim 5, further comprising forming the first recess that extends from a top surface of the passivation layer to a bottom surface of the passivation layer.

### Claim 10 (depends on 5)

The method of claim 5, wherein forming the micro bump includes forming a conductive cap above a conductive bump such that the conductive cap has a higher top surface than the passivation layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
filling the opening with the conductive bump;
conformally forming a second sacrificial layer in the opening;
removing the second sacrificial layer to expose the conductive bump; and
filling the opening with the conductive cap.

### Claim 12 (depends on 5)

The method of claim 5, further comprising forming a conductive cap above the micro bump.

### Claim 13

A method of fabricating a semiconductor device, the method comprising:
forming a conductive pad above a substrate;
forming a passivation layer above the conductive pad;
forming a first sacrificial layer above the passivation layer;
forming an opening in the passivation layer and the first sacrificial layer, above the conductive pad, and that exposes the conductive pad;
forming a micro bump in the opening; and
removing the first sacrificial layer, such that an inner sidewall of the passivation layer faces and is spaced from an outer sidewall of the micro bump.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
forming a second sacrificial layer above the first sacrificial layer;
forming the opening that extends from a top surface of the second sacrificial layer to a bottom surface of the passivation layer through the first sacrificial layer; and
removing the first and second sacrificial layers.

### Claim 15 (depends on 14)

The method of claim 14, further comprising forming a second recess that extends from the top surface of the second sacrificial layer to a position between top and bottom surfaces of the first sacrificial layer.

### Claim 16 (depends on 14)

The method of claim 14, wherein forming the micro bump includes forming a conductive cap above a conductive bump such that the conductive cap has a higher top surface than the passivation layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
filling the opening with a bottom portion of the conductive bump;
conformally forming the second sacrificial layer in the opening;
removing the second sacrificial layer to expose the conductive bump; and
filling the opening with the conductive cap.

### Claim 18 (depends on 17)

The method of claim 17, further comprising, prior to filling the opening with the conductive cap, filling the opening with a top portion of the conductive bump.

### Claim 19 (depends on 13)

The method of claim 13, further comprising forming a first recess that extends from a position between top and bottom surfaces of the first sacrificial layer to a bottom surface of the passivation layer.

### Claim 20 (depends on 13)

The method of claim 13, further comprising forming a conductive cap above the micro bump.