# US 10,319,692 B2 · Semiconductor structure and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,692 B2
- Document ID: US10319692B2
- Status: Granted
- Kind: B2
- Application number: 15/385,100
- Filed: 2016-12-20
- Published: 2017-04-13
- Granted: 2019-06-11
- Earliest claimed: 2014-10-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Yung-Ping Chiang; Chao-Wen Shih; Hao-Yi Tsai; Mirng-Ji Lii
- Web page: https://patentgrep.com/patent/US10319692B2

## CPC

- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 95/062: {involving a dielectric removal step}
- H10W 74/01: Manufacture or treatment
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/654: Top-view layouts
- H10W 70/66: Conductive materials thereof
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/01257: {by reflowing}
- H10W 72/019: {of bond pads}
- H10W 72/01923: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01925: {in solid form}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/283: {Reinforcing structures, e.g. bump collars}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
forming a conductive layer and etching the conductive layer to have an oval area on a semiconductive substrate;
forming a post passivation interconnect (PPI) including an oval landing area on the oval area of the conductive layer;
forming a first conductor on the oval landing area to form an oval-shape conductor;
forming a polymer layer above the semiconductive substrate and the PPI to surround an outer surface of the oval-shape conductor;
polishing the polymer layer and the oval-shape conductor in order to form a planarized surface and expose a polished surface of the oval-shaped conductor; and
forming a second conductor on the polished surface of the oval-shape conductor.

### Claim 2 (depends on 1)

The method of claim 1, further comprising planarizing the top surface of the oval-shape conductor.

### Claim 3 (depends on 1)

The method of claim 1, wherein polishing the polymer layer and the oval-shape conductor further comprises applying a diamond disk on the polymer layer and the oval-shape conductor.

### Claim 4 (depends on 1)

The method of claim 1, wherein receiving the semiconductive substrate comprises chucking the semiconductive substrate on a stage.

### Claim 5 (depends on 1)

The method of claim 1, further comprising measuring a thickness of the polymer layer or the oval-shape conductor after polishing the polymer layer and the first conductor.

### Claim 6 (depends on 1)

The method of claim 1, wherein the oval area of the conductive layer includes an oval portion connected to a second portion via a trace portion on a semiconductive substrate;
the oval landing area of the PPI includes an oval landing portion connected to a second portion via a trace portion formed on the corresponding oval portion, second portion and trace portion, respectively, of the conductive layer; and
the step of forming the first conductor on the oval landing area includes forming the first conductor on the oval landing portion to form the oval-shape conductor.

### Claim 7 (depends on 1)

The method of claim 1, wherein polishing the polymer layer and the oval-shape conductor further comprises applying a slurry on the polymer layer and the oval-shape conductor.

### Claim 8

A method for manufacturing a semiconductor structure, comprising:
receiving a semiconductive substrate with a metal pad thereon;
depositing a layer on the metal pad and above the semiconductive substrate;
removing a portion of the layer, thereby forming an oval area;
electroplating a conductive layer on the layer, thereby forming an oval conductive pad on the oval area;
forming a first conductor on the oval conductive pad;
forming a polymer layer over the conductive layer, thereby surrounding a portion of the first conductor;
partially removing the polymer layer and the first conductor, wherein the first conductor is exposed with an oval-shaped surface; and
disposing a second conductor on the oval-shaped surface of the first conductor.

### Claim 9 (depends on 8)

The method of claim 8, further comprising reflowing the second conductor to form a turning point at an intersection between the first and second conductors.

### Claim 10 (depends on 8)

The method of claim 8, further comprising connecting the second conductor to a printed circuit board (PCB).

### Claim 11 (depends on 8)

The method of claim 8, further comprising applying a slurry on the polymer layer and the first conductor while partially removing the polymer layer and the first conductor.

### Claim 12

A method for manufacturing a semiconductor structure, comprising:
receiving a semiconductive substrate;
forming a plurality of patterned conductive layers having a plurality of oval areas on the semiconductive substrate respectively;
disposing a plurality of post passivation interconnects (PPIs) having a plurality of oval conductive pads on the plurality of oval areas of the plurality of patterned conductive layers respectively;
disposing a polymer layer above the plurality of PPIs and the semiconductive substrate; and
contacting a plurality of conductors with the plurality of PPIs to form a plurality of oval-shape conductors respectively, wherein each of the plurality of oval-shape conductors has a first oval-shape portion and a second oval-shape portion, the first oval-shape is surrounded by the polymer layer, and the second oval-shape portion is protruded from the polymer layer;
wherein the semiconductive substrate has a geometric center, and a longest axis of each of the plurality of oval-shape conductors is towards the geometric center of the semiconductor substrate.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
depositing a conductive layer on the semiconductive substrate;
removing a portion of the conductive layer, thereby forming the plurality of patterned conductive layers;
electroplating the plurality of PPIs on the plurality of patterned conductive layers respectively.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
forming the plurality of oval conductive pads on the plurality of oval areas of the plurality of patterned conductive layers respectively.

### Claim 15 (depends on 12)

The method of claim 12, wherein disposing the plurality of PPIs above the semiconductive substrate comprises:
disposing a conductive layer on the semiconductive substrate;
etching a portion of the conductive layer to form the plurality of PPIs.

### Claim 16 (depends on 15)

The method of claim 15, wherein disposing the plurality of PPIs above the semiconductive substrate further comprises:
forming a plurality of oval conductive pads on the plurality of PPIs respectively.

### Claim 17 (depends on 12)

The method of claim 12, wherein each of the plurality of oval-shape conductors has a shortest axis, and the shortest axis is perpendicular to the longest axis.

### Claim 18 (depends on 12)

The method of claim 12, wherein a top surface of the first oval-shape portion and a top surface of the polymer layer are coplanar.

### Claim 19 (depends on 12)

The method of claim 12, wherein the plurality of oval-shape conductors is placed at a peripheral region of the semiconductor structure.

### Claim 20 (depends on 12)

The method of claim 12, wherein the plurality of the first oval-shape portions are coplanar with the polymer layer, and the plurality of the second oval-shape portions are protruded from the polymer layer.