# US 10,319,691 B2 · Solderless interconnection structure and method of forming same

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- Number: US 10,319,691 B2
- Document ID: US10319691B2
- Status: Granted
- Kind: B2
- Application number: 15/351,184
- Filed: 2016-11-14
- Published: 2017-04-27
- Granted: 2019-06-11
- Earliest claimed: 2012-09-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Wei Lin; Sheng-Yu Wu; Yu-Jen Tseng; Tin-Hao Kuo; Chen-Shien Chen
- Web page: https://patentgrep.com/patent/US10319691B2

## CPC

- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 90/00: Package configurations
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01208: {using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks}
- H10W 72/01212: {at a different location than on the final device, e.g. forming solder preforms}
- H10W 72/01215: {forming coatings}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/07202: {using auxiliary members}
- H10W 72/07221: {Aligning}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07255: {changes in materials}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/235: {of outermost layers of multilayered bumps, e.g. bump coating not being conformal on a bump core}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/2528: {Intermetallic compounds}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/283: {Reinforcing structures, e.g. bump collars}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49144: by metal fusion
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

## Claims

### Claim 1

A method of forming semiconductor device, the method comprising:
mounting a substrate trace on a first substrate, the substrate trace having a first tapering profile with a first distal end, the first distal end having a first width;
forming a metal ladder bump on an under bump metallurgy (UBM) of an integrated circuit, the metal ladder bump having a second tapering profile with a second distal end, the second distal end having a second width greater than the first width; and
coupling the metal ladder bump and the substrate trace together through direct metal-to-metal bonding, the first substrate and the integrated circuit being bonded without use of solder.

### Claim 2 (depends on 1)

The method of claim 1, wherein mounting the substrate trace comprises using an electrolytic plating process.

### Claim 3 (depends on 1)

The method of claim 1, wherein coupling the metal ladder bump and the substrate trace comprises using thermo-compression bonding process, the thermo-compression bonding process comprising:
pressing the first and second distal ends together; and
after the pressing, annealing the metal ladder bump and the substrate trace to bond the first distal end of the metal ladder bump and the second distal end of the substrate trace together.

### Claim 4 (depends on 3)

The method of claim 3, wherein the metal ladder bump and the substrate trace are annealed at a temperature of about 100° C. to about 400° C. for about 1 hour to about 2 hours.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a contact pad on the integrated circuit;
forming one or more insulating layers over the contact pad, the one or more insulating layers having an opening exposing the contact pad; and
forming an under bump metallization in the opening, the under bump metallization extending over an outermost surface of the one or more insulating layers, wherein the metal ladder bump is formed on the under bump metallization.

### Claim 6 (depends on 5)

The method of claim 5, wherein the metal ladder bump extends into the opening in the one or more insulating layers.

### Claim 7 (depends on 6)

The method of claim 6, wherein the metal ladder bump extends closer to the contact pad than an outermost surface of a first insulating layer of the one or more insulating layers, the first insulating layer directly contacting the contact pad.

### Claim 8 (depends on 1)

The method of claim 1, wherein the metal ladder bump is one of a plurality of metal ladder bumps coupled to the substrate trace.

### Claim 9 (depends on 1)

The method of claim 1, wherein no additional conductive materials are disposed between the first and second distal ends after the coupling.

### Claim 10

A method of forming a semiconductor device, the method comprising:
providing a first conductive element and a second conductive element, the first conductive element being on a first substrate and having a first tapered profile with a first distal end, the second conductive element being on an under bump metallurgy (UBM) of an integrated circuit, the second conductive element having a second tapered profile with a second distal end, a first width of the first distal end being less than a second width of the second distal end; and
bonding the first distal end of the first conductive element and the second distal end of the second conductive element, the first conductive element and the second conductive element being bonded without use of solder.

### Claim 11 (depends on 10)

The method of claim 10, wherein a ratio of the first width of the first distal end of the first conductive element to a third width of a first mounted end of the first conductive element is between about 0.75 to about 0.97.

### Claim 12 (depends on 11)

The method of claim 11, wherein a ratio of the second width of the second distal end of the second conductive element to a fourth width of a second mounted end of the second conductive element is between about 0.75 to about 0.97.

### Claim 13 (depends on 10)

The method of claim 10, wherein the bonding comprises performing thermo-compression bonding of the first conductive element to the second conductive element.

### Claim 14 (depends on 13)

The method of claim 13, wherein the bonding comprises annealing to increase a bond strength between the first conductive element and the second conductive element.

### Claim 15 (depends on 14)

The method of claim 14, wherein the annealing is performed at a temperature between 100° C. and 400° C.

### Claim 16 (depends on 15)

The method of claim 15, wherein the annealing is performed for a period of 1 hour to 2 hours.

### Claim 17

A method of forming a semiconductor device, the method comprising:
forming a first conductive element on a first substrate, a first width of the first conductive element decreasing as the first conductive element extends away from the first substrate;
forming an under bump metallurgy (UBM) on a contact element of an integrated circuit;
forming a second conductive element on the UBM, a second width of the second conductive element decreasing as the second conductive element extends away from the integrated circuit, wherein the first width of the first conductive element at a first distal end from the first substrate is less than the second width of the second conductive element at a second distal end from the integrated circuit;
aligning the first conductive element with the second conductive element; and
bonding the first conductive element to the second conductive element without using solder.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a low-k dielectric layer on the integrated circuit;
forming the contact element in the low-k dielectric layer;
forming a first passivation layer over the low-k dielectric layer, the first passivation layer having a first opening exposing the contact element;
forming a second passivation layer over the first passivation layer, the second passivation layer having a second opening exposing the contact element; and
forming the first conductive element extending through the first opening and the second opening.

### Claim 19 (depends on 18)

The method of claim 18, wherein the second passivation layer completely separates the first passivation layer from the first conductive element.

### Claim 20 (depends on 17)

The method of claim 17, wherein a height of the first conductive element is greater than a height of the second conductive element.