# US 10,319,684 B2 · Dummy conductive structures for EMI shielding

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- Number: US 10,319,684 B2
- Document ID: US10319684B2
- Status: Granted
- Kind: B2
- Application number: 15/485,085
- Filed: 2017-04-11
- Published: 2018-10-11
- Granted: 2019-06-11
- Earliest claimed: 2017-04-11
- Assignees: STATS ChipPAC Pte. Ltd.
- Applicants: STATS ChipPAC Pte. Ltd.
- Inventors: InSang Yoon; SeungYong Chai; SoYeon Park
- Web page: https://patentgrep.com/patent/US10319684B2

## CPC

- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/092: {Adapting interconnections, e.g. making engineering changes, repairing}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/0198: {batch processes}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device has a first conductive layer and a second conductive layer. A first portion of the first conductive layer is aligned with a first portion of the second conductive layer. An insulating layer is deposited over the first conductive layer and second conductive layer. A third conductive layer includes a first portion of the third conductive layer vertically aligned with the first portion of the first conductive layer and the first portion of the second conductive layer. An electrical component is disposed over the first conductive layer and second conductive layer. An encapsulant is deposited over the first conductive layer, second conductive layer, and electrical component. A cut is made through the encapsulant, first conductive layer, and second conductive layer. A fourth conductive layer is deposited over side surfaces of the first conductive layer, second conductive layer, and encapsulant.

## Claims

### Claim 1

A method of making a semiconductor device, comprising:
forming a first conductive layer;
forming a conductive pillar over the first conductive layer;
forming a second conductive layer, wherein a first portion of the first conductive layer is vertically aligned with a first portion of the second conductive layer and the conductive pillar;
depositing an encapsulant over the first conductive layer, conductive pillar, and second conductive layer;
cutting through the encapsulant, the first portion of the first conductive layer, the conductive pillar, and the first portion of the second conductive layer; and
depositing a third conductive layer contacting side surfaces of the first conductive layer, conductive pillar, second conductive layer, and encapsulant.

### Claim 2 (depends on 1)

The method of claim 1, further including:
forming the first conductive layer to include a second portion separate from the first portion; and
forming the second conductive layer to include a second portion connecting the first portion of the second conductive layer to the second portion of the first conductive layer.

### Claim 3 (depends on 2)

The method of claim 2, further including disposing a conductive bump on the second portion of the first conductive layer, wherein the conductive bump is electrically connected to the first portion of the first conductive layer through the second conductive layer.

### Claim 4 (depends on 1)

The method of claim 1, further including:
disposing a conductive bump on the first portion of the first conductive layer; and
mounting the semiconductor device to a substrate using the conductive bump.

### Claim 5 (depends on 1)

The method of claim 1, further including:
disposing an electrical component over the first conductive layer and second conductive layer; and
depositing the encapsulant over the electrical component.

### Claim 6 (depends on 1)

The method of claim 1, further including:
forming an insulating layer over the first conductive layer and second conductive layer; and
forming a fourth conductive layer including a first portion of the fourth conductive layer vertically aligned with the first portion of the first conductive layer and the first portion of the second conductive layer.

### Claim 7 (depends on 1)

The method of claim 1, further including disposing a conductive bump on the first conductive layer.

### Claim 8 (depends on 7)

The method of claim 7, further including mounting the semiconductor device to a substrate using the conductive bump.

### Claim 9

A method of making a semiconductor die, comprising:
forming a first conductive layer;
forming a conductive pillar on the first conductive layer;
forming a second conductive layer on the conductive pillar;
cutting through the first conductive layer, conductive pillar and second conductive layer; and
depositing a third conductive layer over side surfaces of the first conductive layer and second conductive layer.

### Claim 10 (depends on 9)

The method of claim 9, further including forming the second conductive layer to include a conductive trace connecting first and second portions of the first conductive layer.

### Claim 11 (depends on 10)

The method of claim 10, further including disposing a conductive bump on the second portion of the first conductive layer.

### Claim 12 (depends on 9)

The method of claim 9, further including disposing a conductive bump on the first conductive layer.

### Claim 13 (depends on 9)

The method of claim 9, further including disposing an electrical component over the first conductive layer and second conductive layer.

### Claim 14 (depends on 9)

The method of claim 9, further including:
forming an insulating layer around the first conductive layer and second conductive layer; and
forming a fourth conductive layer vertically aligned with the first conductive layer and second conductive layer.

### Claim 15

A method of making a semiconductor device, comprising:
forming a first conductive layer;
forming a conductive pillar over the first conductive layer
forming a second conductive layer over the conductive pillar and first conductive layer; and
forming a third conductive layer contacting side surfaces of the first conductive layer, conductive pillar, and second conductive layer.

### Claim 16 (depends on 15)

The method of claim 15, further including:
depositing an encapsulant over the first conductive layer and second conductive layer; and
forming the third conductive layer over a side surface of the encapsulant.

### Claim 17 (depends on 16)

The method of claim 16, further including disposing an electrical component over the second conductive layer in the encapsulant.

### Claim 18 (depends on 15)

The method of claim 15, further including forming the second conductive layer to include a conductive trace connecting two portions of the first conductive layer.

### Claim 19 (depends on 15)

The method of claim 15, further including forming a bump on the first conductive layer.

### Claim 20 (depends on 15)

The method of claim 15, further including:
forming a substrate comprising a plurality of insulating layers and a plurality of conductive layers, wherein the plurality of conductive layers includes the first conductive layer, second conductive layer, and conductive pillar; and
singulating the substrate through the conductive pillar, wherein the plurality of conductive layers occupies an entire height of the substrate within a footprint of the conductive pillar.