# US 10,319,681 B2 · Dummy features in redistribution layers (RDLS) and methods of forming same

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- Number: US 10,319,681 B2
- Document ID: US10319681B2
- Status: Granted
- Kind: B2
- Application number: 16/005,326
- Filed: 2018-06-11
- Published: 2018-10-11
- Granted: 2019-06-11
- Earliest claimed: 2016-04-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Cheng-Hsien Hsieh; Li-Han Hsu; Wei-Cheng Wu; Hsien-Wei Chen; Der-Chyang Yeh; Chi-Hsi Wu; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US10319681B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/016: {using moulds}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.

## Claims

### Claim 1

A device comprising:
a semiconductor die;
a first metallization pattern over the semiconductor die, wherein the first metallization pattern comprises:
a first conductive material encircling a first insulating material in a top down view, wherein the first conductive material encircles a third insulating material in the top down view, a second portion of the first conductive material being disposed between the first insulating material and the third insulating material; and
a first signal line electrically connected to the semiconductor die; and
a second metallization pattern over the first metallization pattern, wherein the second metallization pattern comprises a second conductive material encircling a second insulating material in the top down view, and wherein the second insulating material is disposed directly over a first portion of the first insulating material and a first portion of the first conductive material, and wherein the second conductive material is disposed directly over the third insulating material.

### Claim 2 (depends on 1)

The device of claim 1, wherein the second conductive material is disposed directly over a second portion of the first insulating material and a third portion of the first conductive material.

### Claim 3 (depends on 1)

The device of claim 1 further comprising a via extending through the second metallization pattern, and wherein the via electrically connects the first signal line to a second signal line disposed over the second metallization pattern.

### Claim 4 (depends on 1)

The device of claim 1, wherein the second conductive material completely covers the first signal line in the top down view.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first conductive material or the second conductive material are electrically insulated from any active devices in the semiconductor die.

### Claim 6 (depends on 1)

The device of claim 1, wherein the second insulating material is disposed directly over the third insulating material.

### Claim 7 (depends on 1)

The device of claim 1, wherein the semiconductor die is encapsulated in a molding compound, and wherein the first metallization pattern is disposed over the molding compound.

### Claim 8

A package comprising:
an integrated circuit die encapsulated in an encapsulant;
a first metallization pattern over the integrated circuit die, wherein the first metallization pattern comprises:
a first dummy conductive pattern encircling a first plurality of physically separated dielectric regions; and
a first signal line electrically connected to the integrated circuit die; and
a second metallization pattern over the first metallization pattern, wherein the second metallization pattern comprises a second dummy conductive pattern encircling a second plurality of physically separated dielectric regions, wherein a first line perpendicular to a major surface of the integrated circuit die extends through a first one of the second plurality of physically separated dielectric regions and the first dummy conductive pattern.

### Claim 9 (depends on 8)

The package of claim 8, wherein a second line parallel to the first line extends through a first one of the first plurality of physically separated dielectric regions and the second dummy conductive pattern.

### Claim 10 (depends on 8)

The package of claim 8, wherein the first metallization pattern is disposed in a first dielectric layer comprising the first plurality of physically separated dielectric regions, wherein a portion of the first dielectric layer is disposed over the first metallization pattern, and wherein the portion of the first dielectric layer extends from a first one of the first plurality of physically separated dielectric regions to a second one of the first plurality of physically separated dielectric regions.

### Claim 11 (depends on 8)

The package of claim 8 further comprising:
a third metallization pattern over the second metallization pattern, wherein the third metallization pattern comprises a third dummy conductive pattern encircling a third plurality of physically separated dielectric regions, and wherein the first line extends through the third dummy conductive pattern.

### Claim 12 (depends on 11)

The package of claim 11, wherein the third dummy conductive pattern has a same shape as the first dummy conductive pattern in a top down view.

### Claim 13 (depends on 8)

The package of claim 8, wherein the second dummy conductive pattern comprises a continuous conductive region, and wherein a surface area of the continuous conductive region is greater than a surface area of the first one of the second plurality of physically separated dielectric regions.

### Claim 14 (depends on 13)

The package of claim 13, wherein the continuous conductive region is disposed directly over the first signal line.

### Claim 15 (depends on 14)

The package of claim 14 further comprising a via extending through the continuous conductive region, wherein the via electrically connects the first signal line to a second signal line over the second metallization pattern.

### Claim 16

A method comprising:
encapsulating an integrated circuit die in a molding compound;
forming a first dummy pattern over the integrated circuit die, wherein the first dummy pattern comprises:
a first conductive material; and
a first plurality of holes extending through the first conductive material and arranged in a first grid of first rows and first columns;
depositing a first dielectric layer in the first plurality of holes;
forming a second dummy pattern over the first dielectric layer, wherein the second dummy pattern comprises:
a second conductive material; and
a plurality of second holes extending through the second conductive material and disposed in a second grid of second rows and second columns, wherein the second grid is offset from the first grid; and
depositing a second dielectric layer in the second plurality of holes.

### Claim 17 (depends on 16)

The method of claim 16, further comprising while forming the first dummy pattern, forming a first signal line electrically connected to the integrated circuit die.

### Claim 18 (depends on 16)

The method of claim 16 further comprising:
forming a third dummy pattern over the second dielectric layer, wherein the third dummy pattern comprises:
a third conductive material; and
a plurality of third holes extending through the third conductive material and disposed in a third grid of third rows and third columns, wherein the third grid is offset from the second grid; and
depositing a third dielectric layer in the third plurality of holes.

### Claim 19 (depends on 18)

A method of claim 18, the third grid is aligned with the first grid.

### Claim 20 (depends on 16)

The method of claim 16, the first dielectric layer extends above the first dummy pattern, and wherein the second dielectric layer extends above the second dummy pattern.