# US 10,319,676 B2 · Vertically integrated nanosheet fuse

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- Number: US 10,319,676 B2
- Document ID: US10319676B2
- Status: Granted
- Kind: B2
- Application number: 15/923,009
- Filed: 2018-03-16
- Published: 2018-08-02
- Granted: 2019-06-11
- Earliest claimed: 2017-02-02
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Robin H. Chao; James J. Demarest; Nicolas J. Loubet
- Web page: https://patentgrep.com/patent/US10319676B2

## CPC

- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4451: {Semiconductor materials, e.g. polysilicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/679: {comprising air gaps}
- H10P 50/642: {Chemical etching}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.

## Claims

### Claim 1

A method for forming a semiconductor device, the method comprising:
forming a nanosheet stack on a substrate;
modifying a semiconductor layer of the nanosheet stack, wherein modifying the semiconductor layer such that a lateral etch rate of the modified semiconductor layer when exposed to an etchant is greater than a lateral etch rate of unmodified nanosheet layers of the nanosheet stack;
removing portions of the modified semiconductor layer to form a cavity between upper and lower nanosheets, wherein the upper nanosheet is located above the lower nanosheet; and
forming a silicide region in the upper nanosheet.

### Claim 2 (depends on 1)

The method of claim 1, wherein modifying the semiconductor layer comprises implanting a dopant into the semiconductor layer, and wherein the dopant changes an etch rate of the semiconductor layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the modified semiconductor layer comprises silicon germanium (SiGe), the upper and lower nanosheets comprise silicon (Si), and the dopant comprises Si or germanium (Ge).

### Claim 4 (depends on 3)

The method of claim 3, wherein a concentration of Ge in the modified semiconductor layer is about 10 percent and a break down voltage of the modified semiconductor layer is about 2.9V.

### Claim 5 (depends on 3)

The method of claim 3, wherein a concentration of Ge in the modified semiconductor layer is about 20 percent and a break down voltage of the modified semiconductor layer is about 2.8V.

### Claim 6 (depends on 3)

The method of claim 3, wherein a concentration of Ge in the modified semiconductor layer is about 30 percent and a break down voltage of the modified semiconductor layer is about 2.5V.

### Claim 7 (depends on 1)

The method of claim 1, wherein modifying the semiconductor layer comprises epitaxially growing the semiconductor layer from a material comprising a greater etch rate with respect to an etchant than an etch rate of the upper and lower nanosheets when exposed to the etchant.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the silicide region in the upper nanosheet comprises:
forming a conformal liner over the nanosheet stack and the substrate; and
annealing the conformal liner and the nanosheet stack at a temperature of greater than about 100 degrees Celsius.

### Claim 9 (depends on 8)

The method of claim 8, wherein the conformal liner comprises nickel (Ni), titanium (Ti), or platinum (Pt).

### Claim 10 (depends on 1)

The method of claim 1 further comprising forming a spacer over the nanosheet stack, wherein portions of the spacer fill the cavity.

### Claim 11 (depends on 10)

The method of claim 10 further comprising forming a dielectric region over the nanosheet stack, the spacer, and the substrate.

### Claim 12 (depends on 11)

The method of claim 11 further comprising forming a conductive contact in the dielectric region and on the silicide region in the upper nanosheet.

### Claim 13

A method for forming a semiconductor device, the method comprising:
forming a plurality of nanosheet stacks on a substrate;
modifying a semiconductor layer of the plurality of nanosheet stacks, wherein modifying the semiconductor layer such that a lateral etch rate of the modified semiconductor layer when exposed to an etchant is greater than a lateral etch rate of unmodified nanosheet layers of the nanosheet stack;
removing portions of the modified semiconductor layer to form a cavity between an upper and lower nanosheets of each nanosheet stack; and
forming a silicide region in the upper nanosheet of each nanosheet stack.

### Claim 14 (depends on 13)

The method of claim 13, wherein modifying the semiconductor layers comprises implanting a dopant into the semiconductor layers, and wherein the dopant increases an etch rate of the semiconductor layers.

### Claim 15 (depends on 14)

The method of claim 14, wherein each semiconductor layer comprises silicon germanium (SiGe), each upper and lower nanosheet comprises silicon (Si), and the dopant comprises Si or germanium (Ge).

### Claim 16 (depends on 15)

The method of claim 15, wherein a concentration of Ge in the modified semiconductor layer is about 10 percent and a break down voltage of the modified semiconductor layer is about 2.9V.

### Claim 17

A semiconductor device comprising:
a nanosheet stack formed on a substrate, the nanosheet stack comprising a modified semiconductor layer formed on a nanosheet, wherein the modified semiconductor layer comprises a lateral etch rate of the modified semiconductor layer when exposed to an etchant is greater than a lateral etch rate of other unmodified nanosheet layers of the nanosheet stack;
a silicide layer formed on the substrate and adjacent to the nanosheet stack;
a first conductive contact formed on a silicide region; and
a second conductive contact formed on a surface of the silicide layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the nanosheet comprises a thickness of about 4 nanometers to about 10 nanometers, and wherein the modified semiconductor layer comprises a thickness of about 6 nanometers to about 20 nanometers.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein a concentration of Ge in the modified semiconductor layer is about 20 percent and a break down voltage of the modified semiconductor layer is about 2.8V.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein a concentration of Ge in the modified semiconductor layer is about 30 percent and a break down voltage of the modified semiconductor layer is about 2.5V.