# US 10,319,673 B2 · Low CTE interposer

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- Number: US 10,319,673 B2
- Document ID: US10319673B2
- Status: Granted
- Kind: B2
- Application number: 15/825,968
- Filed: 2017-11-29
- Published: 2018-03-22
- Granted: 2019-06-11
- Earliest claimed: 2011-09-14
- Assignees: Invensas Corporation
- Applicants: Invensas Corporation
- Inventors: Belgacem Haba; Kishor Desai
- Web page: https://patentgrep.com/patent/US10319673B2

## CPC

- H10W 70/635: {Through-vias}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49128: Assembling formed circuit to base
- Y10T 428/24521: with component conforming to contour of nonplanar surface
- Y10T 428/24802: Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

An interconnection component includes a first support portion, a second support portion, a redistribution layer and a passive device, wherein at least one of the first and second support portions is comprised of a semiconductor material. The first support portion includes first and second opposed major surfaces and a plurality of first conductive vias extending through the first support portion substantially perpendicular to major surfaces. The second support portion includes first and second opposed major surfaces and a plurality of second conductive vias extending through the second support portion substantially perpendicular to the first and second major surfaces of the second support. The redistribution layer can be disposed between the second surfaces of the first and second support portions. The passive device can be positioned at least partially within the redistribution layer and electrically connected with one or more of the first conductive vias and the second conductive vias.

## Claims

### Claim 1

An interconnection component, comprising:
a first support portion having first and second opposed major surfaces defining a thickness therebetween and a plurality of first conductive vias extending through the first support portion substantially perpendicular to major surfaces and such that each via has a first end adjacent the first surface and a second end adjacent the second surface;
a second support portion having first and second opposed major surfaces defining a thickness therebetween and a plurality of second conductive vias extending through the second support portion substantially perpendicular to the first and second major surfaces of the second support portion and such that each via has a first end adjacent the first surface and a second end adjacent the second surface of the second support portion;
a redistribution layer disposed between the second surfaces of the first and second support portions, the redistribution layer further including a dielectric layer and routing circuitry embedded in the dielectric layer and electrically connecting the first conductive vias with at least some of the second conductive vias, the routing circuitry including intermediate conductive vias extending at least partially through the dielectric layer;
wherein at least one of the first and second support portions is comprised of a semiconductor material, and
wherein a smallest pitch of the intermediate conductive vias is greater than a largest pitch of the first conductive vias and less than a smallest pitch of the second conductive vias.

### Claim 2 (depends on 1)

The interconnection component of claim 1, further comprising a passive device positioned at least partially within the redistribution layer and electrically connected with one or more of the first conductive vias and the second conductive vias, wherein the passive device is disposed between the second surfaces of the support portions.

### Claim 3 (depends on 1)

The interconnection component of claim 1, further comprising a passive device positioned at least partially within the redistribution layer and electrically connected with one or more of the first conductive vias and the second conductive vias, wherein the passive device is disposed between the second surface of one of the first and second support portions and the first surface of an other of the support portions.

### Claim 4 (depends on 3)

The interconnection component of claim 3, wherein the passive device is disposed between at least some of a plurality of conductive vias of one of the first or second support portions and the first surface of an other of the support portions, such that at least a portion of the passive device is positioned within the other of the support portions.

### Claim 5 (depends on 2)

The interconnection component of claim 2, wherein the intermediate vias extending between the second surfaces of the first and second support portions, the intermediate vias electrically connecting the plurality of first and second conductive vias, and wherein the passive device is disposed between at least some of the intermediate vias.

### Claim 6 (depends on 5)

The interconnection component of claim 5, wherein the intermediate vias have a height that is equal to or greater than a height of the passive device.

### Claim 7 (depends on 2)

The interconnection component of claim 2, wherein the passive device is electrically connected to one of the first and second support portions by redistribution traces extending from each second ends of the plurality of first or second conductive vias to which the passive device is electrically connected.

### Claim 8 (depends on 1)

The interconnection component of claim 1, further including at least one other redistribution layer formed over the first surface of at least one of the first support portion and the second support portion, the redistribution layer including contacts exposed on an outside surface thereof, the contacts being connected with the first conductive vias or the second conductive vias.

### Claim 9 (depends on 2)

The interconnection component of claim 2, wherein the redistribution layer further includes:
first conductive contacts disposed at second ends of the plurality of first conductive vias, the first conductive contacts being connected with the plurality of first conductive vias, and
second conductive contacts disposed at second ends of the second plurality of conductive vias, the second conductive contacts connected with the second conductive vias,
wherein the routing circuitry electrically connects at least some of the first conductive contacts with at least some of the second conductive contacts.

### Claim 10 (depends on 9)

The interconnection component of claim 9, wherein the redistribution layer includes first and second portions, the first portion including the first surface and the first conductive contacts, the second portion including the second surface and the second conductive contacts, wherein each of the first and second portions further includes an intermediate surface and intermediate contacts, wherein the intermediate surfaces face each other and the intermediate contacts are joined together.

### Claim 11 (depends on 1)

The interconnection component of claim 1, wherein a smallest pitch of the first conductive vias is smaller than a smallest pitch of the second conductive vias.

### Claim 12 (depends on 1)

The interconnection component of claim 1, wherein any of the first or second support portions that is of a semiconductor material includes a dielectric lining surrounding portions of the support portion adjacent the conductive vias.

### Claim 13 (depends on 1)

A microelectronic assembly, including:
the interconnection component of claim 1; and
a first microelectronic element having element contacts at a face thereof;
wherein each first ends of the plurality of first conductive vias matches a spatial distribution of the element contacts of the microelectronic element, and the element contacts are joined with the first ends of the plurality of first conductive vias through masses of conductive bonding material.

### Claim 14 (depends on 13)

The microelectronic assembly of claim 13, further including a second microelectronic element having element contacts thereon, wherein an extension of the second support portion extends beyond an edge of the first support portion, the second microelectronic element being mounted on the extension and electrically connected with ones of the plurality of first conductive vias that are exposed on the extension.

### Claim 15 (depends on 14)

The microelectronic assembly of claim 14, further comprising wire bonds, the wire bonds electrically interconnecting the second microelectronic element with ones of the plurality of first conductive vias that are exposed on the extension.

### Claim 16 (depends on 13)

The microelectronic assembly of claim 13, further including a substrate having circuit contacts formed at a surface thereof, the plurality of second conductive vias being electrically connected with the circuit contacts.

### Claim 17 (depends on 16)

The microelectronic assembly of claim 16, further comprising second wire bonds, the second wire bonds connecting ones of the plurality of first conductive vias with some of the circuit contacts.

### Claim 18 (depends on 17)

The microelectronic assembly of claim 17, wherein the second support portion has second contacts exposed at the first surface thereof and electrically connected with the second conductive vias, wherein the second contacts are electrically connected with the circuit contacts.

### Claim 19 (depends on 13)

A system comprising:
a microelectronic assembly according to claim 13 and one or more other electronic components electrically connected to the microelectronic assembly.