# US 10,319,663 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,663 B2 - Document ID: US10319663B2 - Status: Granted - Kind: B2 - Application number: 15/910,420 - Filed: 2018-03-02 - Published: 2019-03-21 - Granted: 2019-06-11 - Earliest claimed: 2017-09-19 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Kenichi Sawanaka - Web page: https://patentgrep.com/patent/US10319663B2 ## CPC - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/251: {Organics} - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 72/30: Die-attach connectors - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/354: {comprising polymers} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/931: {Shapes of bond pads} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor memory device includes a housing having a wall, a circuit board located in the housing and spaced from the wall and extending along the surface of the wall, a memory located on the circuit board, a heat conduction member interposed, and compressed, between the wall and the memory. The wall includes an uneven region comprising contact portions contacting the heat conduction member and recess portions located between the contact portions. The recess portions are recessed inwardly of the wall from the ends of the contact portions in a direction away from the location of the memory. ## Claims ### Claim 1 A semiconductor memory device comprising: a housing having a wall; a circuit board located in the housing and spaced from the wall, and extending along a surface of the wall; a memory located above the circuit board; and a heat conduction member interposed between the wall and the memory, the heat conduction member being formed of an elastic material and elastically compressed therebetween, wherein the wall includes an uneven region comprising contact portions that contact the heat conduction member and recess portions located between the contact portions, the recess portions recessed inwardly of the wall from ends of the contact portions in a direction away from the memory. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein portions of the heat conduction member extend inwardly of the recess portions. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein portions of the contact portions surround at least one of the recess portions. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein the uneven region includes a region in which at least two of the contact portions and at least two of the recess portions are dispersedly arranged with respect to each other. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the uneven region includes a region in which the contact portions and the recess portions are provided in a mesh shaped pattern. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein the uneven region includes a region in which a repetitive pattern, having a unit shape including at least one portion of the contact portions and at least one portion of the recess portions, is located. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, wherein the memory comprises a plurality of corners; and the uneven region further comprises other recess portions facing the corners of the memory, with portions of the heat conduction member extending therebetween. ### Claim 8 (depends on 1) The semiconductor memory device according claim 1, wherein: the memory comprises a plurality of side walls; and other recess portions of the uneven region face, and extend outwardly of, a location of the side walls of the memory, with portions of the heat conduction member extending therebetween. ### Claim 9 (depends on 1) The semiconductor memory device according to claim 1, wherein the wall includes a first surface opposing the circuit board, and a second surface recessed inwardly of the first surface in the direction away from the memory, the contact portion being formed on the second surface; the heat conduction member extends inwardly of the first surface and contacts the second surface; and the recess portions extend inwardly of the second surface. ### Claim 10 A semiconductor device package configured to support one memory device to be located therein or thereon among a plurality of memory devices having a perimeter wall, a first surface, a second surface opposite to the first surface, and a thickness between the first and second surfaces, wherein the thicknesses of different memory devices among the plurality of memory devices are different, comprising: a housing having a wall; a circuit board located in the housing and spaced from the wall, and extending along a surface of the wall; and a heat conduction member formed of an elastic material, wherein the wall includes an uneven region comprising contact portions contacting the heat conduction member and recess portions located between the contact portions, the recess portions recessed inwardly of the wall from ends of the contact portions in a direction away from a mounting location of said one memory device, and the heat conduction member is positioned to be elastically compressed between said one memory device and the wall when said one memory device is mounted in the semiconductor device package. ### Claim 11 (depends on 10) The semiconductor memory device package according to claim 10, wherein portions of the heat conduction member extend inwardly of the recess portions. ### Claim 12 (depends on 10) The semiconductor memory device package according to claim 10, wherein portions of the contact portions surround at least one of the recess portions. ### Claim 13 (depends on 10) The semiconductor memory device package according to claim 10, wherein the uneven region includes a region in which at least two of the contact portions and at least two of the recess portions are dispersedly arranged with respect to each other. ### Claim 14 (depends on 10) The semiconductor memory device package according to claim 10, wherein the uneven region includes a region in which the contact portions and the recess portions are provided in a mesh shaped pattern. ### Claim 15 (depends on 10) The semiconductor memory device package according to claim 10, wherein the uneven region includes a region in which a repetitive pattern, having a unit shape including at least one portion of the contact portions and at least one portion of the recess portions, is located. ### Claim 16 (depends on 10) The semiconductor memory device package according to claim 10, wherein each of the plurality of memory devices comprises a plurality of corners; the uneven region further comprises other recess portions facing a mounting location of the corners of said one memory device; and the heat conduction member extends over the recess portions facing the mounting location of the corners of said one memory device. ### Claim 17 (depends on 10) The semiconductor memory device package according claim 10, wherein each of the plurality of memory devices comprises a plurality of side walls; other recess portions of the uneven region face, and extend outwardly of, a mounting location of a perimeter of said one memory device; and the heat conduction member extends over the mounting location of the perimeter of said one memory device. ### Claim 18 (depends on 10) The semiconductor memory device package according to claim 10, wherein: the wall includes a first wall surface opposing the circuit board and a second wall surface, recessed inwardly of the first wall surface in the direction away from a mounting location of said one memory device, the contact portion being formed on the second wall surface; the heat conduction member extends inwardly of the first wall surface and contacts the wall second surface; and the recess portions extend inwardly of the second wall surface. ### Claim 19 A semiconductor memory device, comprising: a housing having a first wall, the first wall including a plurality of recesses extending inwardly thereof; a compressible heat transfer member comprising a first surface and a second surface opposite to the first surface, the first surface thereof contacting the first wall, the compressible heat transfer member being formed of an elastic material, elastically compressed, and having a first thickness between the first and second surfaces thereof less than a thickness of the compressible heat transfer member in a non-compressed state; a memory having a third surface and a fourth surface opposite to the third surface, and a second thickness between the third and fourth surfaces, the third surface contacting the second surface of the compressible heat transfer member; and a circuit board facing the fourth surface of the memory and spaced from the first wall by a gap distance, wherein the sum of the first thickness of the heat transfer member and the second thickness of the memory is equal to the gap distance. ### Claim 20 (depends on 19) The semiconductor memory device of claim 19, wherein a portion of the compressible heat transfer member extends into at least one of the plurality of recesses.