# US 10,319,654 B1 · Integrated chip scale packages > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,654 B1 - Document ID: US10319654B1 - Status: Granted - Kind: B1 - Application number: 15/829,288 - Filed: 2017-12-01 - Published: 2019-06-06 - Granted: 2019-06-11 - Earliest claimed: 2017-12-01 - Assignees: Cubic Corporation - Applicants: Nuvotronics, Inc. - Inventors: J. Robert Reid - Web page: https://patentgrep.com/patent/US10319654B1 ## CPC - H10W 70/68: Shapes or dispositions thereof - H01P 3/06: Coaxial lines - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 72/00: Interconnections or connectors in packages - H10W 72/071: {Connecting or disconnecting} - H10W 72/072: {of bump connectors} - H10W 72/075: {of bond wires} - H10W 76/153: having interconnections in passages through the insulating or insulated base - H10W 44/206: {Wires} - H10W 44/216: {Waveguides, e.g. strip lines} - H10W 44/251: {for monolithic microwave integrated circuits [MMIC]} - H10W 72/073: {of die-attach connectors} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/354: {comprising polymers} - H10W 72/5366: {the bond wires having kinks} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B) ## Abstract Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package. ## Claims ### Claim 1 A chip scale package, comprising a carrier composed of a plurality of sequential layers stacked together as a continuous stack to provide a monolithic carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create an at least partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the conductive stub comprises a plurality of sequential layers stacked together as a continuous stack. ### Claim 2 A chip scale package, comprising a carrier composed of a plurality of sequential layers stacked together as a continuous stack to provide a monolithic carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create an at least partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the dielectric support comprises a first portion embedded in the conductive stub. ### Claim 3 (depends on 1) The chip scale package according to claim 1, wherein the dielectric support comprises a second portion embedded in the carrier at the passageway. ### Claim 4 (depends on 1) The chip scale package according to claim 1, wherein the dielectric support comprises an annular disk. ### Claim 5 (depends on 1) The chip scale package according to claim 1, comprising an electronic chip disposed therein electrically connected to the stub. ### Claim 6 (depends on 1) The chip scale package according to claim 1, comprising a chip disposed therein electrically connected to the stub. ### Claim 7 (depends on 1) The chip scale package according to claim 1, comprising an electronic chip disposed therein electrically connected to the stub by a wirebond. ### Claim 8 (depends on 1) The chip scale package according to claim 1, comprising an electronic chip disposed therein electrically connected to the stub by a solder bump. ### Claim 9 A chip scale package, comprising a carrier composed of a plurality of sequential layers stacked together as a continuous stack to provide a monolithic carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create an at least partially hermetic seal at the passageway between the exterior and interior of the carrier, comprising a coaxial connector mounted thereto, the coaxial connector comprising a center conductor electrically connected to the conductive stub and comprising an outer conductor electrically connected to the carrier body to provide a coaxial to coaxial connection. ### Claim 10 (depends on 1) The chip scale package according to claim 1, wherein the continuous stacks of the carrier and conductive stub comprise metal. ### Claim 11 (depends on 1) The chip scale package according to claim 1, comprising a lid hermetically sealed thereto to hermetically seal the chip in the carrier. ### Claim 12 (depends on 1) The chip scale package according to claim 1, comprising a plurality of passageways extending between the exterior and interior of the carrier, the passageways each having a respective conductive stub extending therethrough, each stub suspended in the respective passageway by a dielectric support, each stub and respective support cooperating to create a hermetic seal at the respective passageway between the exterior and interior of the carrier. ### Claim 13 (depends on 1) The chip scale package according to claim 1, wherein the passageway comprises a plurality of conductive stubs disposed therein, each stub hermetically sealed in the passageway. ### Claim 14 A method of forming a chip scale package component, comprising: depositing a plurality of layers, wherein the layers comprise one or more of a conductive material and a dielectric material, thereby forming a structure comprising: a carrier composed of a plurality of sequential layers of the conductive material stacked together as a continuous stack to provide a monolithic conductive carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create a hermetic or partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the conductive stub comprises a plurality of sequential layers stacked together as a continuous stack. ### Claim 15 (depends on 14) The method according to claim 14, comprising electrically connecting an electronic chip to the stub within the interior of the carrier. ### Claim 16 (depends on 15) The method according to claim 15, comprising hermetically sealing a lid onto the carrier to hermetically seal the chip in the carrier. ### Claim 17 A method of forming a chip scale package component, comprising: depositing a plurality of layers, wherein the layers comprise one or more of a conductive material and a dielectric material, thereby forming a structure comprising: a carrier composed of a plurality of sequential layers of the conductive material stacked together as a continuous stack to provide a monolithic conductive carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create a hermetic or partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the dielectric support comprises a first portion embedded in the conductive stub. ### Claim 18 (depends on 14) The method according to claim 14, wherein the dielectric support comprises a second portion embedded in the carrier at the passageway. ### Claim 19 (depends on 14) The method according to claim 14, wherein the dielectric support comprises an annular disk. ### Claim 20 (depends on 15) The method according to claim 15, wherein the electronic chip is electrically connected to the stub by a wirebond. ### Claim 21 (depends on 15) The method according to claim 15, wherein the electronic chip is electrically connected to the stub by a solder bump. ### Claim 22 A method of forming a chip scale package component, comprising: depositing a plurality of layers, wherein the layers comprise one or more of a conductive material and a dielectric material, thereby forming a structure comprising: a carrier composed of a plurality of sequential layers of the conductive material stacked together as a continuous stack to provide a monolithic conductive carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create a hermetic or partially hermetic seal at the passageway between the exterior and interior of the carrier, comprising mounting a coaxial connector to the carrier, the coaxial connector comprising a center conductor electrically connected to the conductive stub and comprising an outer conductor electrically connected to the carrier body to provide a coaxial to coaxial connection. ### Claim 23 (depends on 14) The method according to claim 14, wherein the continuous stacks of the carrier and conductive stub comprise metal. ### Claim 24 (depends on 14) The method according to claim 14, wherein the carrier comprises a plurality of passageways extending between the exterior and interior of the carrier, the passageways each having a respective conductive stub extending therethrough, each stub suspended in the respective passageway by a dielectric support, each stub and respective support cooperating to create a hermetic seal at the respective passageway between the exterior and interior of the carrier. ### Claim 25 (depends on 14) The method according to claim 14, wherein the passageway comprises a plurality of conductive stubs disposed therein, each stub hermetically sealed in the passageway.