# US 10,319,653 B2 · Semiconductor apparatus, stacked semiconductor apparatus, encapsulated stacked-semiconductor apparatus, and method for manufacturing the same

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- Number: US 10,319,653 B2
- Document ID: US10319653B2
- Status: Granted
- Kind: B2
- Application number: 15/126,172
- Filed: 2015-03-12
- Published: 2017-04-13
- Granted: 2019-06-11
- Earliest claimed: 2014-03-31
- Assignees: Shin-Etsu Chemical Co., Ltd.
- Applicants: Shin-Etsu Chemical Co., Ltd.
- Inventors: Katsuya Takemura; Kyoko Soga; Satoshi Asai; Kazunori Kondo; Michihiro Sugo; Hideto Kato
- Web page: https://patentgrep.com/patent/US10319653B2

## CPC

- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- B23K 1/0016: {Soldering of electronic components}
- B29C 70/78: Moulding material on one side only of the preformed part
- B29C 70/882: {partly or totally electrically conductive, e.g. for EMI shielding (conductive floors or floor coverings H05F3/025; EMI shielding in general H05K9/00)}
- C23C 14/042: {using masks}
- C23C 14/34: Sputtering
- C23C 14/58: After-treatment
- C25D 3/60: containing more than 50% by weight of tin
- C25D 5/022: {using masking means}
- C25D 5/48: After-treatment of electroplated surfaces
- C25D 5/505: {of electroplated tin coatings, e.g. by melting}
- C25D 7/123: {Semiconductors first coated with a seed layer or a conductive layer}
- H10P 14/6342: {Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- B29K 2063/00: Use of {EP, i.e.} epoxy resins {or derivatives thereof}, as moulding material
- B29K 2083/00: Use of polymers having silicon, with or without sulfur, nitrogen, oxygen, or carbon only, in the main chain, as moulding material
- B29K 2105/20: Inserts
- B29K 2995/0005: Conductive
- B29L 2031/3493: {Moulded interconnect devices, i.e. moulded articles provided with integrated circuit traces}
- H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components}
- H05K 2201/10515: Stacked components
- H05K 2201/1053: Mounted components directly electrically connected to each other, i.e. not via the PCB
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B29C: SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING (making preforms B29B11/00; making laminated products by combining previously unconnected layers which become one product whose layers will remain together B32B37/00 - B32B41/00)
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B29K: INDEXING SCHEME ASSOCIATED WITH SUBCLASSES B29B, B29C OR B29D, RELATING TO MOULDING MATERIALS OR TO MATERIALS FOR {MOULDS, } REINFORCEMENTS, FILLERS OR PREFORMED PARTS, e.g. INSERTS
- B29L: INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A semiconductor apparatus includes a semiconductor device, on-semiconductor-device metal pad and metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first insulating layer on which the semiconductor device is placed, a second insulating layer formed on the semiconductor device, a third insulating layer formed on the second layer. The metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second layer, penetrates the second layer from its upper surface, and is electrically connected to the through electrode at an lower surface of the second layer, and an under-semiconductor-device metal interconnect is between the first layer and the semiconductor device, and the under-semiconductor-device metal interconnect is electrically connected to the metal interconnect at the lower surface of the second layer.

## Claims

### Claim 1

A method for manufacturing a semiconductor apparatus, comprising the steps of:
(1) applying a temporary adhesive to a supporting substrate and forming a first insulating layer having a thickness of 1 to 20 μm on the temporary adhesive, wherein the first insulating layer consists of a photo-curable resin layer composed of a resist composition;
(2) patterning the first insulating layer by lithography via a mask to form a hole pattern for forming a through electrode, and then baking the first insulating layer to cure the first insulating layer;
(3) forming a seed layer on the first insulting layer by sputtering, then filling the hole pattern for forming the through electrode by plating to form a metal interconnect to be connected to the through electrode, and simultaneously forming an under-semiconductor-device metal interconnect;
(4) die bonding a semiconductor device having a height of 20 to 100 μm to the cured first insulating layer, on which the under-semiconductor-device metal interconnect is formed, with a die bonding agent, wherein an exposed electrode pad is provided on an upper surface of the semiconductor device;
(5) preparing photo-curable dry films comprising a photo-curable resin layer sandwiched between a supporting film and a protective film, wherein the photo-curable resin layer has a thickness of 5 to 100 μm and is composed of a resist composition;
(6) forming a second insulating layer by laminating the photo-curable resin layer of one of the photo-curable dry film such that the semiconductor device die-bonded on the first insulating layer is covered with the photo-curable resin layer;
(7) patterning the second insulating layer by lithography via a mask to simultaneously form an opening on the electrode pad, an opening for forming a metal interconnect that penetrates the second insulating layer on the metal interconnect to be connected to the through electrode, and an opening for forming the through electrode, and then baking the second insulating layer to cure the second insulating layer;
(8) after curing, forming a seed layer by sputtering, then filling the opening on the electrode pad, the opening for forming the metal interconnect that penetrates the second insulating layer, and the opening for forming the through electrode by plating to respectively form an on-semiconductor-device metal pad, the metal interconnect that penetrates the second insulating layer, and the through electrode, and connecting the on-semiconductor-device metal pad and the metal interconnect that penetrates the second insulating layer, which are formed by plating, via a metal interconnect formed by plating;
(9) after forming the metal interconnects, forming a third insulating layer by laminating the photo-curable resin layer of the other photo-curable dry film or applying the same resist composition as used in the photo-curable dry film by spin coating;
(10) patterning the third insulating layer by lithography via a mask to form an opening on the through electrode, and then baking the third insulating layer to cure the third insulating layer; and
(11) after curing, forming a solder bump in the opening on the through electrode.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor apparatus according to claim 1, wherein the resist composition constituting the photo-curable resin layer of the photo-curable dry film prepared in the step (5) is a chemically amplified negative resist composition containing:
(A) a silicone skeleton-containing polymer compound having a repeating unit shown by the following general formula (1) and having a weight average molecular weight of 3,000 to 500,000
wherein R1 to R4 may be the same or different and represent a monovalent hydrocarbon group having 1 to 8 carbon atoms; “m” is an integer of 1 to 100; “a”, “b”, “c”, and “d” are each 0 or a positive number, and “a”, “b”, “c”, and “d” are not simultaneously 0, provided that a+b+c+d=1; X represents an organic group shown by the following general formula (2); and Y represents an organic group shown by the following general formula (3);
wherein Z represents a divalent organic group selected from any of
“n” is 0 or 1; R5 and R6 each represent an alkyl group or alkoxy group having 1 to 4 carbon atoms and may be the same or different from each other; and “k” is 0, 1, or 2;
wherein V represents a divalent organic group selected from any of
“p” is 0 or 1; R7 and R8 each represent an alkyl group or alkoxy group having 1 to 4 carbon atoms and may be the same or different from each other; and “h” is 0, 1, or 2;
(B) one or more crosslinking agents selected from an amino condensate modified with formaldehyde or formaldehyde-alcohol and a phenol compound having on average two or more methylol groups or alkoxymethylol groups per molecule;
(C) a photo acid generator capable of generating an acid by decomposition with light having a wavelength of 190 to 500 nm; and
(D) a solvent.

### Claim 3 (depends on 1)

The method for manufacturing a semiconductor apparatus according to claim 1, wherein the step (6) includes mechanically pressing the second insulating layer.

### Claim 4 (depends on 2)

The method for manufacturing a semiconductor apparatus according to claim 2, wherein the step (6) includes mechanically pressing the second insulating layer.

### Claim 5 (depends on 1)

The method for manufacturing a semiconductor apparatus according to claim 1, wherein the step (11) includes
forming an on-through-electrode metal pad in the opening on the through electrode by plating, and
forming a solder ball on the on-through-electrode metal pad for the solder bump.

### Claim 6 (depends on 2)

The method for manufacturing a semiconductor apparatus according to claim 2, wherein the step (11) includes
forming an on-through-electrode metal pad in the opening on the through electrode by plating, and
forming a solder ball on the on-through-electrode metal pad for the solder bump.

### Claim 7 (depends on 1)

The method for manufacturing a semiconductor apparatus according to claim 1, wherein plating to form the through electrode in the step (8) includes plating with SnAg,
the step (10) includes patterning to form the opening on the through electrode such that the SnAg plating is uncovered, and
the step (11) includes melting the SnAg plating and thereby forming a protruding electrode in the opening on the through electrode for the solder bump.

### Claim 8 (depends on 1)

The method for manufacturing a semiconductor apparatus according to claim 1, further comprising the steps of:
after the step (11), removing the supporting substrate, which has been temporarily bonded to the first insulating layer in the step (1); and
after removing the substrate, dicing the semiconductor apparatus into individual pieces.

### Claim 9 (depends on 8)

A method for manufacturing a stacked semiconductor apparatus, comprising stacking a plurality of individual semiconductor apparatuses obtained by dicing in the manufacturing method according to claim 8, while putting an insulting resin layer between the individual semiconductor apparatuses such that the individual semiconductor apparatuses are electrically connected through the solder bump.

### Claim 10 (depends on 9)

A method for manufacturing an encapsulated stacked-semiconductor apparatus, comprising the steps of:
placing a stacked semiconductor apparatus manufactured by the manufacturing method according to claim 9 on a substrate having an electric circuit; and
encapsulating the stacked semiconductor apparatus placed on the substrate with an insulating encapsulating resin layer.