# US 10,319,650 B2 · Semiconductor package having redistribution pattern and passivation patterns and method of fabricating the same

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- Number: US 10,319,650 B2
- Document ID: US10319650B2
- Status: Granted
- Kind: B2
- Application number: 15/603,859
- Filed: 2017-05-24
- Published: 2018-03-15
- Granted: 2019-06-11
- Earliest claimed: 2016-09-13
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jongyoun Kim; Seokhyun Lee
- Web page: https://patentgrep.com/patent/US10319650B2

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/722: {between stacked chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.

## Claims

### Claim 1

A semiconductor package comprising:
a redistribution substrate; and
a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof,
wherein the redistribution substrate comprises,
a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad,
a second passivation pattern outside the first passivation pattern on the one surface, the second passivation pattern laterally spaced apart from the first passivation pattern,
a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern,
wherein a level of the first passivation pattern is same as a level of the second passivation pattern.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the redistribution pattern includes an isolation region filling a space between the first and second passivation patterns.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the redistribution substrate further comprises:
an insulating pattern between the conductive pad and the second passivation pattern.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein:
the redistribution pattern includes an isolation region, which fills a space between the first and second passivation patterns, and
a portion of the insulating pattern is between the conductive pad and the isolation region.

### Claim 5 (depends on 3)

The semiconductor package of claim 3, wherein:
the redistribution pattern fills a space between the first and second passivation patterns; and
a portion of the insulating pattern is between the conductive pad and a portion of the first passivation pattern.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein a portion of the second passivation pattern is on the conductive pad.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein an outer sidewall of the first passivation pattern is inside an edge of the conductive pad when viewed from a plan view.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein an outer sidewall of the first passivation pattern is outside an edge of the conductive pad when viewed from a plan view.

### Claim 9

A semiconductor package comprising:
a substrate including a first conductive pad on one surface thereof; and
a semiconductor chip on the substrate, the semiconductor chip including a second conductive pad on one surface thereof,
wherein the substrate further comprises,
a redistribution pattern electrically connecting the first conductive pad to the second conductive pad, and
a first passivation pattern and a second passivation pattern on the second conductive pad, the first and second passivation patterns laterally spaced apart from each other, the redistribution pattern covering the first passivation pattern.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein the redistribution pattern is in contact with the second conductive pad of the semiconductor chip.

### Claim 11 (depends on 9)

The semiconductor package of claim 9, wherein the redistribution pattern includes an isolation region filling a space between the first and second passivation patterns.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, further comprising:
an insulating pattern between the second conductive pad of the semiconductor chip and the isolation region.

### Claim 13 (depends on 9)

The semiconductor package of claim 9, further comprising:
a shielding pattern extending from the redistribution pattern and filling a space between the first and second passivation patterns, the shielding pattern having a lower hygroscopic property than the redistribution pattern.

### Claim 14 (depends on 13)

The semiconductor package of claim 13, further comprising:
an insulating pattern between the second conductive pad of the semiconductor chip and the shielding pattern.

### Claim 15

A semiconductor package comprising:
a semiconductor chip having a conductive pad on one surface thereof; and
a redistribution substrate having the semiconductor chip thereon, the redistribution substrate including,
a first passivation pattern covering a first portion of the conductive pad, and
a redistribution pattern covering a second portion of the conductive pad that is exposed by the first passivation pattern, and surrounding an outside of the first passivation pattern,
wherein the first passivation pattern covers an edge region and a sidewall of the conductive pad and a surface of the redistribution substrate exposed by the conductive pad.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, further comprising:
a second passivation pattern spaced apart from the first passivation pattern by a portion of the redistribution pattern interposed therebetween, the second passivation pattern covering a sidewall of the first passivation pattern.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein the second passivation pattern is entirely on a surface of the redistribution substrate exposed by the conductive pad.