# US 10,319,645 B2 · Method for forming a semiconductor structure containing high mobility semiconductor channel materials

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- Number: US 10,319,645 B2
- Document ID: US10319645B2
- Status: Granted
- Kind: B2
- Application number: 15/494,099
- Filed: 2017-04-21
- Published: 2017-08-10
- Granted: 2019-06-11
- Earliest claimed: 2015-06-16
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Pouya Hashemi; Ali Khakifirooz; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US10319645B2

## CPC

- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/274: {using seed materials}
- H10P 14/276: {Lateral overgrowth}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2921: {being crystalline insulating materials}
- H10P 14/2922: {being non-crystalline insulating materials, e.g. glass or polymers}
- H10P 14/2924: {Structures}
- H10P 14/3414: {being group IIIA-VIA materials}
- H10P 50/242: {of Group IV materials}
- H10P 50/642: {Chemical etching}
- H10P 50/646: {of Group III-V materials}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to provide an undercut region in the germanium-containing layer. A III-V compound semiconductor material is grown within the undercut region by utilizing an aspect ratio trapping growth process. Next, portions of the III-V compound semiconductor material are removed to provide III-V compound semiconductor material portions located between remaining portions of the germanium-containing layer.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing semiconductor material layer;
forming hard mask material portions having an opening that physically exposes a portion of the germanium-containing semiconductor material layer on the substrate;
etching through the opening to remove the physically exposed portion of the germanium-containing semiconductor material layer and to provide an undercut region in the germanium-containing semiconductor material layer, the undercut region is located between two remaining portions of the germanium-containing semiconductor material layer;
growing a III-V compound semiconductor material within the undercut region and laterally outwards from sidewall surfaces of the two remaining portions of the germanium-containing semiconductor material layer; and
removing portions of the III-V compound semiconductor material to provide III-V compound semiconductor material portions located between the two remaining portions of the germanium-containing semiconductor material layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the germanium-containing semiconductor material layer is selected from unalloyed germanium, a silicon germanium alloy and a multilayered stack of germanium and a silicon germanium alloy.

### Claim 3 (depends on 1)

The method of claim 1, wherein the etching comprises a lateral etch.

### Claim 4 (depends on 3)

The method of claim 3, wherein the lateral etch comprises hydrogen peroxide or gaseous HCl.

### Claim 5 (depends on 3)

The method of claim 3, wherein after the etching, one of the hard mask material portions overhangs one of the two remaining portions of the germanium-containing semiconductor material layer, and another of the hard mask material portions overhangs another of the two remaining portions of the germanium-containing semiconductor material layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the removing the portions of the III-V compound semiconductor material comprises forming trench isolation openings that extend to topmost surface of the insulator layer, and forming a trench dielectric structure within each of the trench isolation openings.

### Claim 7 (depends on 6)

The method of claim 6, wherein the forming the trench dielectric structure comprises filling each trench isolation opening with a trench dielectric material, and removing an upper portion of the trench dielectric material and each of the hard mask material portions.

### Claim 8 (depends on 7)

The method of claim 7, further comprising forming a first functional gate structure on a surface of each of the III-V compound semiconductor material portions and forming a second functional gate structure on a surface of each of the two remaining portions of the germanium-containing semiconductor material layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the removing the portions of the III-V compound semiconductor material comprises forming trench isolation openings that extend into the handle substrate, and forming a trench dielectric structure within each of the trench isolation openings.

### Claim 10 (depends on 9)

The method of claim 9, wherein the forming the trench dielectric structure comprises filling each trench isolation opening with a trench dielectric material, and removing an upper portion of the trench dielectric material and each of the hard mask material portions.

### Claim 11 (depends on 10)

The method of claim 10, further comprising forming a first functional gate structure on a surface of each of the III-V compound semiconductor material portions and forming a second functional gate structure on a surface of each of the two remaining portions of the germanium-containing semiconductor material layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein prior to forming the first and second functional gate structures, each of the III-V compound semiconductor material portions and each of the two remaining portions of the germanium-containing semiconductor material layer are patterning into fins.

### Claim 13 (depends on 1)

The method of claim 1, wherein the III-V compound semiconductor material has defects that terminate at an overhanging portion of a bottommost surface of each hard mask material portion.

### Claim 14 (depends on 13)

The method of claim 13, wherein the defects are threading dislocations.

### Claim 15 (depends on 9)

The method of claim 9, wherein the removing the portions of the III-V compound semiconductor material comprises forming the trench isolation openings that extend into the handle substrate provides a pedestal portion to the handle substrate.

### Claim 16 (depends on 15)

The method of claim 15, wherein dopants are present in the pedestal portion.

### Claim 17 (depends on 16)

The method of claim 16, wherein the dopants comprise n-type dopants or p-type dopants.

### Claim 18 (depends on 16)

The method of claim 16, further comprising applying a back gate bias so as to convert the pedestal portion into a semiconductor back gate pedestal portion.

### Claim 19

A method of forming a semiconductor structure, the method comprising:
providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing semiconductor material layer;
forming hard mask material portions having an opening that physically exposes a portion of the germanium-containing semiconductor material layer on the substrate;
etching through the opening to remove the physically exposed portion of the germanium-containing semiconductor material layer and to provide an undercut region in the germanium-containing semiconductor material layer, the undercut region is located between two remaining portions of the germanium-containing semiconductor material layer;
growing a III-V compound semiconductor material within the undercut region and laterally outwards from sidewall surfaces of the two remaining portions of the germanium-containing semiconductor material layer, wherein the III-V compound semiconductor material contains defect regions that are present in the undercut region; and
removing portions of the III-V compound semiconductor material including the entirety of each defect containing region to provide III-V compound semiconductor material portions located between the two remaining portions of the germanium-containing semiconductor material layer.