# US 10,319,644 B2 · Method for manufacturing semiconductor structure

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- Number: US 10,319,644 B2
- Document ID: US10319644B2
- Status: Granted
- Kind: B2
- Application number: 15/460,894
- Filed: 2017-03-16
- Published: 2017-06-29
- Granted: 2019-06-11
- Earliest claimed: 2015-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Man-Ho Kwan; Fu-Wei Yao; Ru-Yi Su; Chun Lin Tsai; Alexander Kalnitsky
- Web page: https://patentgrep.com/patent/US10319644B2

## CPC

- H10D 84/05: using Group III-V technology
- H10D 62/114: {PN junction isolations}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3416: {Nitrides}
- H10P 14/3418: {Phosphides}
- H10P 14/3421: {Arsenides}
- H10P 14/3422: {Antimonides}
- H10P 30/206: {into Group III-V semiconductors}
- H10P 30/21: {of electrically active species}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10D 8/25: Zener diodes
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In some embodiments, a semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate of a first material system, the substrate having a first device region and a second device region;
defining an active region only in the first device region, the active region comprising a transistor having a channel; and
forming a layer of a second material system on the substrate, the second material system being different from the first material system; and
defining an isolation region in a portion of the layer over the first device region and at least across an entire width of the first device region by an implantation operation.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming an interconnect penetrating through the layer of the second material system, the interconnect connecting the active region to a conductive layer over the first device region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the implantation operation comprises implanting dopants with a negative charge.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
the operation of forming the layer of a second material system on the substrate comprises:
forming a first bandgap layer on the substrate; and
forming a second bandgap layer on the first bandgap layer; and
the operation of defining the isolation region in a portion of the layer over the first device region comprises:
defining the isolation region across an interface of the first bandgap layer and the second bandgap layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein a bandgap of the second bandgap layer is greater than a bandgap of the first bandgap layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first material system comprises Si, and the second material system comprises III-V material.

### Claim 7 (depends on 2)

The method of claim 2, wherein the forming the interconnect penetrating through the layer of the second material system comprises forming a through-GaN-via.

### Claim 8 (depends on 1)

The method of claim 1, wherein defining the active region is prior to defining the isolation region.

### Claim 9

A method for manufacturing a semiconductor structure, comprising:
providing a silicon substrate having a first device region and a second device region;
defining a first active region only in the first device region, the active region comprising a transistor having a channel;
forming a III-V layer on the silicon substrate after the defining the first active region, comprising:
depositing a first bandgap layer over the first device region; and
depositing a second bandgap layer over the first bandgap layer;
defining an isolation region across an interface of the first bandgap layer and the second bandgap layer by an implantation operation; and
forming an interconnect penetrating through the isolation region.

### Claim 10 (depends on 9)

The method of claim 9, wherein the forming the III—V layer on the silicon substrate comprises:
depositing the first bandgap layer over the first device region and the second device region.

### Claim 11 (depends on 9)

The method of claim 9, wherein the implantation operation comprises implanting dopants with a negative charge.

### Claim 12 (depends on 10)

The method of claim 10, wherein the defining the isolation region comprises implanting dopants with a negative charge.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
forming the interconnect penetrating through the III-V layer, the interconnect connecting the first active region to a conductive layer over the first device region.

### Claim 14 (depends on 10)

The method of claim 10, whereby depositing the first bandgap layer and the second bandgap layer forms a second active region above the second device region.

### Claim 15 (depends on 9)

The method of claim 9, further comprising:
forming the interconnect penetrating through the III-V layer directly over the first device region; and
forming a conductive layer over the III-V layer,
wherein the interconnect connects the first active region to the conductive layer.

### Claim 16 (depends on 10)

The method of claim 10, wherein a bandgap of the second bandgap layer is greater than a bandgap of the first bandgap layer.

### Claim 17 (depends on 9)

The method of claim 9, wherein defining the first active region is prior to defining the isolation region.

### Claim 18

A method for manufacturing a semiconductor structure, comprising:
providing a silicon substrate having a first device region and a second device region;
defining a first active region in the first device region;
forming a first bandgap layer on the silicon substrate;
forming a second bandgap layer on the first bandgap layer;
defining an isolation region across an interface between the first bandgap layer and the second bandgap layer by an ion implantation operation;
forming an interconnect penetrating through the isolation region;
patterning a conductive layer directly on a top surface of the second bandgap layer, the conductive layer disposed over the first device region and the second device region after the patterning.

### Claim 19 (depends on 18)

The method of claim 18, whereby forming the first bandgap layer and the second bandgap layer forms a second active region above the second device region.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
forming the interconnect penetrating through the first bandgap layer and the second bandgap layer, the interconnect being directly over the first device region.