# US 10,319,643 B1 · Vertical FET with strained channel

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- Number: US 10,319,643 B1
- Document ID: US10319643B1
- Status: Granted
- Kind: B1
- Application number: 15/890,699
- Filed: 2018-02-07
- Granted: 2019-06-11
- Earliest claimed: 2018-02-07
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Choonghyun Lee; Kangguo Cheng; Juntao Li; Shogo Mochizuki
- Web page: https://patentgrep.com/patent/US10319643B1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3242: {Structure}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3454: {Amorphous}
- H10P 50/242: {of Group IV materials}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes depositing a strain relaxed buffer (SRB) layer over a substrate; recessing the SRB layer on a first region of the structure; and forming a first semiconductor layer on the first region of the structure and depositing one or more mandrels over the first semiconductor layer of the first region of the structure. The method further includes depositing a spacer layer over the one or more mandrels, the spacer layer including vertical portions and horizontal portions; and removing the one or more mandrels and the horizontal portions of the spacer layer. The method further includes performing a reactive ion etch to remove material unprotected by the spacer to form a first channel for a p-type vertical field effect transistor from the first semiconductor layer. The first channel has a compressive strain.

## Claims

### Claim 1

A method for forming a semiconductor structure, the method comprising:
depositing a strain relaxed buffer (SRB) layer over a substrate;
recessing the SRB layer on a first region of the structure;
forming a first semiconductor layer on the first region of the structure;
depositing one or more mandrels over the first semiconductor layer of the first region of the structure;
depositing a spacer layer over the one or more mandrels, the spacer layer comprising vertical portions and horizontal portions;
removing the one or more mandrels and the horizontal portions of the spacer layer; and
removing material unprotected by the spacer to form a first channel for a p-type vertical field effect transistor from the first semiconductor layer, wherein the first channel includes a compressive strain.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the semiconductor structure is a complementary semiconductor; and
the method further comprises:
depositing one or more mandrels over the SRB layer of a second region of the structure;
patterning one or more fins of SRB layer in the second region of the structure, using the one or more mandrels as a mask; and
epitaxially growing a second semiconductor layer on the exposed sidewalls of the one or more fins;
wherein performing a reactive ion etch to remove material unprotected by the spacer form a second channel for an n-type vertical field effect transistor from the second semiconductor layer;
wherein the second channel is unstrained.

### Claim 3 (depends on 2)

The method of claim 2 further comprising placing a block mask on the second region to prevent formation of the first semiconductor layer on the second region.

### Claim 4 (depends on 3)

The method of claim 3 further comprising filling a region between gaps between the second semiconductor layer on the exposed sidewalls of the one or more fins with amorphous silicon.

### Claim 5 (depends on 2)

The method of claim 2, wherein the second semiconductor layer comprises silicon.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first semiconductor layer comprises silicon.

### Claim 7 (depends on 1)

The method of claim 1, wherein:
the substrate comprises silicon; and
the SRB layer comprises silicon germanium.

### Claim 8 (depends on 1)

The method of claim 1, wherein the mandrel comprises a nitride.

### Claim 9 (depends on 1)

The method of claim 1, wherein the mandrel comprises an oxide.

### Claim 10 (depends on 1)

The method of claim 1, wherein the spacer layer comprises a dielectric material.

### Claim 11

A semiconductor structure, comprising:
a substrate:
a strain relaxed buffer (SRB) layer over the substrate;
a first channel for a p-type vertical field effect transistor; wherein the first channel includes a compressive strain; and
a second channel for an n-type vertical field effect transistor; wherein the second channel is unstrained;
wherein the first channel is formed by a method comprising:
depositing a first semiconductor layer over the SRB layer in a first region of the structure;
depositing a first mandrel over the first semiconductor layer;
depositing a spacer layer over the first mandrel, the spacer layer comprising vertical portions and horizontal portions;
removing the first mandrel and the horizontal portions of the spacer layer; and
performing a reactive ion etch to remove material unprotected by remaining portions of the spacer layer to form the first channel from the first semiconductor layer;
wherein the second channel is formed by a method comprising:
depositing a second mandrel over the SRB layer in a second region of the structure;
patterning one or more fins from the SRB layer in the second region of the structure, using the second mandrel as a mask;
epitaxially growing a second semiconductor layer on sidewalls of the one or more fins;
depositing the spacer layer over the second mandrel; and
performing a reactive ion etch to remove material unprotected by the spacer layer to form the second channel from the second semiconductor layer.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the method further comprises
placing a block mask on the second region to prevent formation of the first semiconductor layer on the second region.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, further comprising filling a region between gaps between the second semiconductor layer on the exposed sidewalls of the one or more fins with amorphous silicon.

### Claim 14 (depends on 11)

The semiconductor structure of claim 11, wherein the second semiconductor layer comprises silicon.

### Claim 15 (depends on 11)

The semiconductor structure of claim 11, wherein the first semiconductor layer comprises silicon.

### Claim 16 (depends on 11)

The semiconductor structure of claim 11, wherein:
the substrate comprises silicon; and
the SRB layer comprises silicon germanium.

### Claim 17

A method for forming a complementary semiconductor structure, the method comprising:
depositing a strain relaxed buffer (SRB) layer over a substrate;
recessing the SRB layer on a first region of the structure;
forming a first semiconductor layer on the first region of the structure;
depositing one or more mandrels over the first semiconductor layer of the first region of the structure;
depositing a spacer layer over the one or more mandrels, the spacer layer comprising vertical portions and horizontal portions;
removing the one or more mandrels and the horizontal portions of the spacer layer;
removing material unprotected by the spacer to form a first channel for a p-type vertical field effect transistor from the first semiconductor layer;
depositing one or more mandrels over the SRB layer of a second region of the structure;
patterning one or more fins of SRB layer in the second region of the structure, using the one or more mandrels as a mask;
epitaxially growing a second semiconductor layer on the exposed sidewalls of the one or more fins; and
removing material unprotected by the spacer to form a second channel for an n-type vertical field effect transistor from the second semiconductor layer; wherein
the first channel has a compressive strain; and
the second channel is unstrained.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
placing a block mask on the second region to prevent formation of the first semiconductor layer on the second region; and
filling a region between gaps between the second semiconductor layer on the exposed sidewalls of the one or more fins with amorphous silicon.

### Claim 19 (depends on 17)

The method of claim 17, wherein:
the first semiconductor layer comprises silicon;
the second semiconductor layer comprises silicon.