# US 10,319,642 B2 · Heterogeneous integration of 3D SI and III-V vertical nanowire structures for mixed signal circuits fabrication

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- Number: US 10,319,642 B2
- Document ID: US10319642B2
- Status: Granted
- Kind: B2
- Application number: 15/667,305
- Filed: 2017-08-02
- Published: 2018-01-11
- Granted: 2019-06-11
- Earliest claimed: 2016-07-08
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Suraj Kumar Patil; Ajey P. Jacob
- Web page: https://patentgrep.com/patent/US10319642B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/837: {comprising vertical IGFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/279: {Vapour-liquid-solid growth}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2907: {being Group IIIA-VA materials}
- H10P 14/2908: {Nitrides}
- H10P 14/2909: {Phosphides}
- H10P 14/2911: {Arsenides}
- H10P 14/2925: {Surface structures}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3414: {being group IIIA-VIA materials}
- H10P 14/3462: {Nanowires}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.

## Claims

### Claim 1

A method comprising:
forming a substrate stack including an amorphous silicon (a-Si) followed by n or p doping or doped polysilicon (poly-Si) layer and a silicon oxycarbide (SiOC) layer;
forming first and second groups of trenches in the substrate stack down to the doped a-Si/poly-Si layer of the substrate stack;
forming a first mask over the second group of trenches;
forming silicon (Si), germanium (Ge) or silicon germanium (SixGe1-x) nanowires in the first group of trenches;
removing the first mask and forming a second mask over the Si, Ge, or SixGe1-x nanowires;
forming III-V nanowires in the second group of trenches;
removing the second mask; and
planarizing the Si, Ge, or SixGe1-x and III-V nanowires down to the SiOC layer.

### Claim 2 (depends on 1)

The method according to claim 1, comprising forming the substrate stack by:
forming a Si substrate;
forming a buffer oxide layer over the Si substrate;
forming the a-Si or doped poly-Si layer over the oxide layer;
forming a first silicon nitride (SiN) layer over the a-Si or doped poly-Si layer;
forming the SiOC layer over the first SiN layer; and
forming a second SiN layer over the SiOC layer.

### Claim 3 (depends on 1)

The method according to claim 1, comprising forming the trenches within the substrate stack by:
self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), direct surface assembly (nanoimprint), or extreme ultraviolet (EUV) lithography.

### Claim 4 (depends on 1)

The method according to claim 1, comprising forming the Si, Ge, or SixGe1-x nanowires by:
depositing a nickel (Ni) or gold (Au) nanoparticle in each of the first group of trenches by self-assembly in sol-gel or by metal organic chemical vapor deposition (MOCVD) or atomic layer growth (ALD); and
growing the Si, Ge, or SixGe1-x nanowires to a desired height.

### Claim 5 (depends on 4)

The method according to claim 4, comprising pre-cleaning the first group of trenches prior to depositing the Ni or Au nanoparticle.

### Claim 6 (depends on 1)

The method according to claim 1, comprising forming the III-V nanowires by:
depositing an aluminum (Al), Ni, or gallium (Ga) nanoparticle in each of the second group of trenches by self-assembly in sol-gel or by MOCVD, ALD;
growing the III-V nanowires to a desired height by a metal catalyst vertical vapor liquid solid (VLS) growth or chemical vapor deposition (CVD) growth with in-situ doping during growth; and
removing the second mask prior to planarizing the Si, Ge, or SixGe1-x and III-V nanowires.

### Claim 7 (depends on 6)

The method according to claim 6, comprising pre-cleaning the second group of trenches prior to depositing the Al, Ni, or Ga nanoparticle.

### Claim 8 (depends on 6)

The method according to claim 6, comprising planarizing the Si, Ge, or SixGe1-x and III-V nanowires by chemical mechanical planarization (CMP).

### Claim 9 (depends on 1)

The method according to claim 1, comprising forming the III-V nanowires of a combination of indium phosphide (InP), indium arsenide (InAs), gallium nitride (GaN), or gallium arsenide (GaAs).

### Claim 10 (depends on 1)

The method according to claim 1, wherein the metal catalyst comprises Ni, Al, Au, silver (Ag), titanium (Ti), erbium (Er), platinum (Pt), palladium (Pd), indium (In), Tin (Sn), antimony (Sb), Zirconium (Zr), vanadium (V), hafnium (Hf), tungsten (W), cobalt (Co), tantalum (Ta), lanthanum (La), ruthenium (Ru), molybdenum (Mo), Ga, or iron (Fe).

### Claim 11

A method comprising:
forming a substrate stack including an amorphous silicon (a-Si) followed by n or p doping or doped polysilicon (poly-Si) layer and a silicon oxycarbide (SiOC) layer;
forming first and second groups of trenches by self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), direct surface assembly (nanoimprint), or extreme ultraviolet (EUV) lithography in the substrate stack down to the doped a-Si/poly-Si layer of the substrate stack;
forming a first mask over the second group of trenches;
forming silicon (Si), germanium (Ge) or silicon germanium (SixGe1-x) nanowires in the first group of trenches by VLS or chemical vapor deposition (CVD) process with in-situ doping;
removing the first mask and forming a second mask over the Si, Ge, or SixGe1-x nanowires;
forming III-V nanowires of a combination of indium phosphide (InP), indium arsenide (InAs), gallium nitride (GaN), or gallium arsenide (GaAs) in the second group of trenches by a metal catalyst VLS or CVD growth with in-situ doping;
removing the second mask; and
planarizing the Si, Ge, or SixGe1-x and III-V nanowires down to the SiOC layer by chemical mechanical planarization (CMP).

### Claim 12 (depends on 11)

The method according to claim 11, comprising forming the substrate stack by:
forming a Si substrate;
forming a buffer oxide layer over the Si substrate;
forming the a-Si or doped poly-Si layer over the oxide layer;
forming a first silicon nitride (SiN) layer over the a-Si or doped poly-Si layer;
forming the SiOC layer over the first SiN layer; and
forming a second SiN layer over the SiOC layer.

### Claim 13 (depends on 11)

The method according to claim 11, comprising forming the Si, Ge, or SixGe1-x nanowires by:
pre-cleaning the first group of trenches;
depositing a nickel (Ni) or gold (Au) nanoparticle in each of the first group of trenches by self-assembly in sol-gel or by metal organic chemical vapor deposition (MOCVD) or atomic layer growth (ALD); and
growing the Si, Ge, or SixGe1-x nanowires to a desired height.

### Claim 14 (depends on 11)

The method according to claim 11, comprising forming the III-V nanowires by:
pre-cleaning the second group of trenches;
depositing an aluminum (Al), Ni, or gallium (Ga) nanoparticle in each of the second group of trenches by self-assembly in sol-gel or by MOCVD, ALD;
growing the III-V nanowires to a desired height by a metal catalyst vertical vapor liquid solid (VLS) growth or chemical vapor deposition (CVD) growth with in-situ doping during growth; and
removing the second mask prior to planarizing the Si, Ge, or SixGe1-x and III-V nanowires.