# US 10,319,638 B2 · Self-aligned contact cap

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- Number: US 10,319,638 B2
- Document ID: US10319638B2
- Status: Granted
- Kind: B2
- Application number: 15/879,035
- Filed: 2018-01-24
- Published: 2018-06-14
- Granted: 2019-06-11
- Earliest claimed: 2016-07-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Peng Xu
- Web page: https://patentgrep.com/patent/US10319638B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/679: {comprising air gaps}
- H10W 20/0698: {Local interconnections}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot and recessing a dielectric fill that encapsulates the gate structures to a position below a top of the gate cap. An extension layer is deposited over the dielectric fill and the top of the gate cap and is planarized to the top of the gate cap. The extension layer is expanded to form a profile growth layer that is thicker than the extension layer and creates a second divot over the gate cap. A top cap is formed in the second divot to provide a cap with a thickness of the gate cap and the top cap.

## Claims

### Claim 1

A method for forming a semiconductor device, comprising:
recessing a dielectric fill that encapsulates a gate structure to a position below a top of a gate cap formed in a first divot;
depositing an extension layer over the dielectric fill and the top of the gate cap;
planarizing the extension layer to the top of the gate cap; and
expanding the extension layer to form a profile growth layer that is thicker than the extension layer and to create a second divot extending to a top surface of the gate cap.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein the first divot is formed by recessing a gate conductor in the gate structure without interfacing with a seam formed within the gate conductor.

### Claim 3 (depends on 1)

The method as recited in claim 1, wherein depositing the extension layer includes depositing a polysilicon layer.

### Claim 4 (depends on 3)

The method as recited in claim 3, wherein expanding the extension layer includes oxidizing the polysilicon layer to form the profile growth layer having second divots formed therein.

### Claim 5 (depends on 4)

The method as recited in claim 4, further comprising isotropically etching the profile growth layer to shape the second divots.

### Claim 6 (depends on 1)

The method as recited in claim 1, wherein expanding the extension layer includes expanding the extension layer by about 100% in thickness.

### Claim 7

A method for forming a semiconductor device, comprising:
replacing a dummy gate of a gate structure with a replacement gate having a gate conductor formed by deposition;
recessing the gate conductor in the gate structure to form a first divot that is shallow enough not to interfere with a potential seam formed during gate conductor formation;
recessing a dielectric fill that encapsulates the gate structure to a position below a top of a gate cap formed in the first divot;
depositing an extension layer over the dielectric fill and the top of the gate cap;
planarizing the extension layer to the top of the gate cap; and
expanding the extension layer to form a profile growth layer that is thicker than the extension layer and to create a second divot extending to a top surface of the gate cap.

### Claim 8 (depends on 7)

The method as recited in claim 7, wherein depositing the extension layer includes depositing a polysilicon layer.

### Claim 9 (depends on 8)

The method as recited in claim 8, wherein expanding the extension layer includes oxidizing the polysilicon layer to form the profile growth layer having second divots formed therein.

### Claim 10 (depends on 9)

The method as recited in claim 9, further comprising isotropically etching the profile growth layer to shape the second divots.

### Claim 11 (depends on 8)

The method as recited in claim 8, wherein expanding the extension layer includes expanding the extension layer by about 100% in thickness.