# US 10,319,634 B2 · Semiconductor device having MIM capacitor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,634 B2 - Document ID: US10319634B2 - Status: Granted - Kind: B2 - Application number: 15/688,325 - Filed: 2017-08-28 - Published: 2018-03-01 - Granted: 2019-06-11 - Earliest claimed: 2016-08-30 - Assignees: Sumitomo Electric Device Innovations, Inc. - Applicants: Sumitomo Electric Device Innovations, Inc. - Inventors: Fumio Yamada - Web page: https://patentgrep.com/patent/US10319634B2 ## CPC - H10W 20/046: {the barrier, adhesion or liner layers being associated with interconnections of capacitors} - H10D 1/042: {using deposition processes to form electrode extensions} - H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)} - H10D 1/716: {having vertical extensions} - H10D 84/212: {of only capacitors} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/4424: {Copper alloys} - H10W 20/496: {Capacitor integral with wiring layers} - H10W 72/90: Bond pads, in general - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device that provides a pad electrically connected to the metal layer and a capacitor connected to the pad is disclosed. The semiconductor device provides an insulating film between the lower electrode of the capacitor and the pad. Because the insulating film protects and isolates the lower electrode from etching of the substrate via and deposition of the via metal, the lower electrode avoids voids or vacancies during formation of the via and the via metal. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; a semiconductor layer provided on the substrate, the substrate having a via piercing from a bottom of the substrate to a top of the semiconductor layer, the via providing a via metal therein; a pad provided on the semiconductor layer and electrically connected with the via metal, the pad fully covering the via and having a periphery that does not overlap the via; a first insulating film covering the pad; a capacitor provided on the first insulating film, the capacitor including a lower electrode, a second insulating film, and an upper electrode from a side of the first insulating film; and an interconnection that is connected with the periphery of the pad, the interconnection surrounding the pad and extending to an area where the pad exposes the semiconductor layer, wherein the first insulating film is sandwiched between the pad and the lower electrode of the capacitor. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the via metal fills the via. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the via metal covers a side of the via and extends to a back surface of the substrate. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first insulating film extends to an outside of the pad and covers the semiconductor layer on the substrate. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the capacitor is fully overlapped by the first insulating film, and the first insulating film is fully overlapped by the pad. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the interconnection is connected with the lower electrode in an area outside of the upper electrode, and wherein the interconnection is connected with the pad in an area outside of the capacitor where the area outside of the capacitor forms the periphery of the pad. ### Claim 7 (depends on 1) The semiconductor device of claim 1, further including another interconnection that connects the upper electrode with the pad, wherein the another interconnection is connected with the pad in an area outside of the capacitor, the area outside of the capacitor forming the periphery of the pad. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the second insulating film extends outside of the capacitor and covers sides of the lower electrode and a top of the pad. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the pad contains gold (Au). ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the first insulating film is made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxy-nitride (SiON). ### Claim 11 A semiconductor device, comprising: a substrate; a semiconductor layer provided on the substrate, the substrate having a via piercing from a bottom of the substrate to a top of the semiconductor layer, the via providing a via metal therein; a pad provided on the semiconductor layer and electrically connected with the via metal, the pad fully covering the via and having a periphery that does not overlap the via; a first insulating film covering the pad; and a capacitor provided on the first insulating film, the capacitor including a lower electrode, a second insulating film, and an upper electrode from a side of the first insulating film, wherein the first insulating film is sandwiched between the pad and the lower electrode of the capacitor, and wherein the second insulating film extends outside of the capacitor and covers sides of the lower electrode and a top of the pad. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the via metal fills the via. ### Claim 13 (depends on 11) The semiconductor device of claim 11, wherein the via metal covers a side of the via and extends to a back surface of the substrate. ### Claim 14 (depends on 11) The semiconductor device of claim 11, wherein the pad contains gold (Au). ### Claim 15 (depends on 11) The semiconductor device of claim 11, wherein the first insulating film is made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxy-nitride (SiON).