# US 10,319,630 B2 · Encapsulated damascene interconnect structure for integrated circuits

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- Number: US 10,319,630 B2
- Document ID: US10319630B2
- Status: Granted
- Kind: B2
- Application number: 13/629,411
- Filed: 2012-09-27
- Published: 2014-03-27
- Granted: 2019-06-11
- Earliest claimed: 2012-09-27
- Assignees: STMicroelectronics S.r.l.; International Business Machines Corporation
- Applicants: STMicroelectronics, Inc.; International Business Machines Corporation
- Inventors: John H. Zhang; Lawrence A. Clevenger; Carl Radens; Yiheng Xu
- Web page: https://patentgrep.com/patent/US10319630B2

## CPC

- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/076: {in via holes or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/421: {Skip vias, i.e. vias that do not connect all metallization layers that they pass through}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.

## Claims

### Claim 1

A device comprising:
a semiconductor substrate;
a plurality of transistors in the semiconductor substrate;
a first intermetal dielectric layer overlying the semiconductor substrate;
a plurality of first metal tracks overlying the first intermetal dielectric layer;
a first protective dielectric layer encapsulating each of the first metal tracks on at least three sides;
a second intermetal dielectric layer overlying the first metal tracks and the first protective dielectric layer;
a plurality of second metal tracks overlying the second intermetal dielectric layer;
a second protective dielectric layer encapsulating each of the second metal tracks on at least three sides, the first and second intermetal dielectric layers being selectively etchable with respect to the first and second protective dielectric layers; and
a plurality of L-shaped unitary vias extending between selected ones of the first and second metal tracks, each L-shaped unitary via having a first section of a first substantially uniform width directly below a second section of a second, different, substantially uniform width.

### Claim 2 (depends on 1)

The device of claim 1 wherein the first protective dielectric layer forms at least one sidewall that determines the first substantially uniform width of each L-shaped unitary via.

### Claim 3 (depends on 1)

The device of claim 1 wherein a first L-shaped unitary via of the plurality of L-shaped unitary vias is integral with at least one of the second metal tracks.

### Claim 4 (depends on 3)

The device of claim 3 comprising:
a third intermetal dielectric layer overlying the second intermetal dielectric layer;
a plurality of third metal tracks overlying the third intermetal dielectric layer;
a third protective dielectric layer encapsulating each of the third metal tracks on at least three sides;
a fourth intermetal dielectric layer overlying the plurality of third metal tracks and the third protective dielectric layer;
a plurality of fourth metal tracks overlying the fourth intermetal dielectric layer; and
a fourth protective dielectric layer encapsulating each of the fourth metal tracks on at least three sides.

### Claim 5 (depends on 4)

The device of claim 4 comprising a second unitary via in the third and fourth intermetal dielectric layers that includes the first L-shaped unitary via.

### Claim 6 (depends on 5)

The device of claim 5 wherein the second unitary via electrically couples at least one of the fourth metal tracks to at least one of the second metal tracks.

### Claim 7 (depends on 1)

The device of claim 1 wherein the first protective dielectric layer includes silicon nitride.

### Claim 8 (depends on 7)

The device of claim 7 wherein the first protective dielectric layer includes carbon.

### Claim 9 (depends on 8)

The device of claim 8 wherein the first protective dielectric layer has a thickness less than 50 nm and the first intermetal dielectric layer has a thickness greater than 100 nm.

### Claim 10 (depends on 1)

The device of claim 1 wherein the first substantially uniform width is less than the second substantially uniform width.

### Claim 11

A device comprising:
a semiconductor substrate;
a first intermetal dielectric layer overlying the semiconductor substrate;
a first metal track overlying the first intermetal dielectric layer;
a first protective dielectric layer encapsulating the first metal track on at least three sides;
a second intermetal dielectric layer overlying the first metal track and the first protective dielectric layer;
a second metal track on the second intermetal dielectric layer;
a second protective dielectric layer encapsulating the second metal track on at least three sides; and
a unitary via in the first and second intermetal dielectric layers, the unitary via having a first section of a first substantially uniform width directly below a second section of a second, different, substantially uniform width.

### Claim 12 (depends on 11)

The device of claim 11 wherein the unitary via couples the second metal track with the first metal track.

### Claim 13 (depends on 12)

The device of claim 12 wherein the unitary via and the second metal track are integral with each other.

### Claim 14 (depends on 11)

The device of claim 11 wherein the first and second metal tracks together with the unitary via form a double foot branch interconnect structure.

### Claim 15 (depends on 11)

The device of claim 11 wherein a section of the unitary via having a narrow width is located underneath a wider section of the unitary via.

### Claim 16

A device comprising:
a semiconductor substrate;
a plurality of transistors in the semiconductor substrate;
a first intermetal dielectric layer overlying the semiconductor substrate;
a plurality of first metal tracks overlying the first intermetal dielectric layer;
a first protective dielectric layer encapsulating each of the first metal tracks on at least three sides;
a second intermetal dielectric layer overlying the first metal tracks and the first protective dielectric layer;
a plurality of second metal tracks overlying the second intermetal dielectric layer; a second protective dielectric layer encapsulating each of the second metal tracks on at least three sides, the first and second intermetal dielectric layers being selectively etchable with respect to the first and second protective dielectric layers;
a plurality of unitary vias coupling selected ones of the first and second metal tracks, the unitary vias having sections of different widths, the first protective dielectric layer forming at least one sidewall that determines a first width of the unitary via;
a first conductive plug in the unitary via, the first conductive plug being integral with the at least one of the second metal tracks;
a third intermetal dielectric layer overlying the second intermetal dielectric layer;
a plurality of third metal tracks overlying the third intermetal dielectric layer;
a third protective dielectric layer encapsulating each of the third metal tracks on at least three sides;
a fourth intermetal dielectric layer overlying the plurality of third metal tracks and the third protective dielectric layer;
a plurality of fourth metal tracks overlying the fourth intermetal dielectric layer;
a fourth protective dielectric layer encapsulating each of the fourth metal tracks on at least three sides; and
a unitary via in the third and fourth intermetal dielectric layers exposing the first conductive plug.

### Claim 17 (depends on 16)

The device of claim 16, further comprising a second conductive plug in the unitary via, the second conductive plug electrically coupling selected ones of the plurality of fourth metal tracks and the plurality of second metal tracks.

### Claim 18

A device, comprising:
a substrate;
a first metal track on the substrate;
a second metal track on the substrate, the second metal track being spaced apart from the first metal track;
a dielectric layer having a first portion and a second portion, the first portion of the dielectric layer completely surrounding four sides of the first metal track, the second portion of the dielectric layer being on the second metal track and having an opening in which the second portion of the dielectric layer is not on a part of a surface of the second metal track; and
a unitary via having a vertical narrow portion extending between the first metal track and the second metal track and a horizontal wide portion that couples to the vertical narrow portion, the horizontal wide portion of the unitary via being positioned in the opening and being physically and electrically coupled to the part of the surface of the second metal track.

### Claim 19 (depends on 18)

The device of claim 18 wherein the unitary via is L-shaped.