# US 10,319,629 B1 · Skip via for metal interconnects

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- Number: US 10,319,629 B1
- Document ID: US10319629B1
- Status: Granted
- Kind: B1
- Application number: 15/973,630
- Filed: 2018-05-08
- Granted: 2019-06-11
- Earliest claimed: 2018-05-08
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chih-Chao Yang; Lawrence A. Clevenger; Brent A. Anderson; Nicholas A. Lanzillo
- Web page: https://patentgrep.com/patent/US10319629B1

## CPC

- H10W 20/076: {in via holes or trenches}
- H10P 50/283: {by chemical means}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/0552: {by diffusing metallic dopants to react with dielectrics}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/421: {Skip vias, i.e. vias that do not connect all metallization layers that they pass through}
- H10W 20/48: Insulating materials thereof
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein a portion of the intervening metallization level (MX+1) is in a pathway of the skip via.

## Claims

### Claim 1

A method of forming a skip-via structure in a semiconductor device, the method comprising:
forming a first interconnect level (Mx) comprising depositing a first dielectric layer on a substrate including one or more semiconductor devices, forming at least one first metal conductor in the first dielectric layer, wherein the at least one metal conductor and the first dielectric have coplanar surfaces, and depositing a first cap layer on the coplanar surfaces;
forming a second interconnect level (Mx+1) comprising depositing a second dielectric layer on the first cap layer, forming at least one second metal conductor in the second dielectric layer, wherein the second metal conductor comprises a second cap layer on a top surface thereof and a liner layer that collectively encapsulate the second metal conductor;
forming a third interconnect level (Mx+2) comprising depositing a third dielectric layer on the second interconnect level;
forming a via opening in the second and third dielectric layers to the first metal conductor, wherein the via opening exposes a portion of the second cap layer, a sidewall of the second metal conductor, and a portion of the first cap layer;
removing the first cap layer at a bottom of the via opening to expose a surface of the first metal conductor;
depositing a spacer layer on sidewalls of the via opening including the sidewall of the second metal conductor; and
filling the via opening with a metal conductor, wherein the second metal conductor in the second interconnect level is electrically isolated from the filled via opening extending from the third interconnect level to the first metal conductor of the first interconnect level, and wherein the first and second cap layers have different etch selectivities.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the via opening comprises selectively etching the first cap layer at a bottom of the via opening without removing the second cap layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein filling the via opening with the metal conductor comprises depositing a barrier layer on the sidewalls defining the via opening prior to filling the via opening with the metal conductor.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the via opening further comprises forming one or more openings in the third dielectric layer and filling the one or more openings with the metal when filling the via opening.

### Claim 5 (depends on 1)

The method of claim 1, wherein the one or more openings comprise a trench, a via, or combinations thereof.

### Claim 6 (depends on 1)

The method of claim 1, wherein the one or more openings define a third metal conductor in the third interconnect level.

### Claim 7 (depends on 1)

The method of claim 1 further comprising self-forming an insulator on the sidewall of the second metal conductor, wherein self-forming the insulator comprises reacting an alloying element in the second metal conductor with at least the oxygen in the spacer layer to form an oxide of the alloying element on the sidewall of the second metal conductor.

### Claim 8

A semiconductor device comprising:
a first interconnect level (Mx) comprising a first dielectric layer, a first metal conductor, and a first capping layer overlaying the first metal conductor;
a second interconnect level (Mx+1) on the first interconnect layer comprising a second dielectric layer, a second metal conductor, and a second capping layer overlaying the second metal conductor, wherein the second capping layer has a different etch selectivity relative to the first capping layer;
a third interconnect level (Mx+2) on the second interconnect level comprising a third dielectric layer, and a third metal conductor; and
a skip via opening filled with a metal extending from the third interconnect level to the first interconnect level, wherein a portion of the second metal conductor including a sidewall thereof in the second interconnect level is in a path of the skip via opening and is electrically isolated from the filled metal via opening.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the skip via opening further comprises a spacer insulator on vertical sidewalls defining the filled metal via opening.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the exposed sidewall of the second metal conductor in the second interconnect level further comprises a self-formed barrier layer thereon.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the self-formed barrier layer comprises a reaction product between an alloying element in the second metal conductor and at least oxygen in the spacer insulator.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the self-formed barrier layer comprises MnSixOy, wherein x:y=1:3 to 3:5.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the first, second and third metal conductor and the metal filled via opening comprise Cu, Co, Al, AlCu, Ti, TiN, Ta, TaN, W, WN, MoN, Pt, Pd, Os, Ru, IrO2, ReO2, ReO3, alloys thereof, or mixtures thereof.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the skip via opening further comprises a liner on sidewalls defining the skip via opening.

### Claim 15 (depends on 8)

The semiconductor device of claim 8, wherein the skip via opening further comprise spacer material on sidewalls defining the skip via opening, and a liner layer on the spacer material.

### Claim 16

A semiconductor device comprising:
a first interconnect level (Mx) comprising a first dielectric layer, a first metal conductor, and a first capping layer overlaying the first metal conductor and a first liner layer encapsulating the first metal conductor;
a second interconnect level (Mx+1) on the first interconnect layer comprising a second dielectric layer, a second metal conductor, and a second capping layer overlaying the second metal conductor and a second liner layer encapsulating the second metal conductor, wherein the second capping layer has a different etch selectivity relative to the first capping layer;
a third interconnect level (Mx+2) on the second interconnect level comprising a third dielectric layer, and a third metal conductor; and
a skip via including a metal extending from the third interconnect level to the first interconnect level, wherein a portion of the second metal conductor including the second capping layer and a sidewall thereof in the second interconnect level is in a path of the skip via during formation thereof, wherein the sidewall comprises a self-formed barrier layer effective in combination with the capping layer to be electrically isolated from the skip via.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the skip via opening further comprise spacer material on sidewalls defining the skip via, and a liner layer on the spacer material.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the self-formed barrier layer comprises MnSixOy, wherein x:y=1:3 to 3:5.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the first, second and third metal conductor and the metal filled via opening comprise Cu, Co, Al, AlCu, Ti, TiN, Ta, TaN, W, WN, MoN, Pt, Pd, Os, Ru, IrO2, ReO2, ReO3, alloys thereof, or mixtures thereof.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the self-formed barrier layer comprises a reaction product between an alloying element in the second metal conductor and at least oxygen in the spacer insulator.