# US 10,319,625 B2 · Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures

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- Number: US 10,319,625 B2
- Document ID: US10319625B2
- Status: Granted
- Kind: B2
- Application number: 15/772,711
- Filed: 2015-12-22
- Published: 2018-11-08
- Granted: 2019-06-11
- Earliest claimed: 2015-12-22
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Paul A. Nyhus; Mohit K. Haran; Charles H. Wallace; Robert M. Bigwood; Deepak S. Rao; Alexander F. Kaplan
- Web page: https://patentgrep.com/patent/US10319625B2

## CPC

- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/087: {involving multiple stacked pre-patterned masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

## Claims

### Claim 1

A method of fabricating an interconnect structure for a semiconductor die, the method comprising:
forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate;
forming an inter-layer dielectric layer above the metallization layer;
forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer;
forming a second grating pattern above the first grating pattern;
patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer; and
forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
removing the first grating pattern and the second grating pattern prior to forming the metal vias and metal lines in the via locations and line regions.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming a pattern accumulation layer between the first grating pattern and the second grating pattern.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
patterning the pattern accumulation layer twice prior to forming the via locations in the inter-layer dielectric layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the first grating pattern comprises using a pitch division processing scheme.

### Claim 6

A method of fabricating an interconnect structure for a semiconductor die, the method comprising:
forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate;
forming an inter-layer dielectric layer above the metallization layer;
forming a grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer, wherein intersections of the grating pattern and the alternating metal lines and dielectric lines of the lower metallization layer define possible via locations for a metallization layer;
forming a pattern accumulation layer above the grating pattern;
patterning the pattern accumulation layer to form a patterned memory layer;
patterning the inter-layer dielectric layer using the grating pattern and the patterned memory layer to form via locations and line regions in the inter-layer dielectric layer; and
forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
removing the grating pattern and the patterned memory layer prior to forming the metal vias and metal lines in the via locations and line regions.

### Claim 8 (depends on 6)

The method of claim 6, wherein patterning the pattern accumulation layer comprises patterning the pattern accumulation layer twice prior to forming the form via locations in the inter-layer dielectric layer.

### Claim 9 (depends on 6)

The method of claim 6, wherein forming the grating pattern comprises using a pitch division processing scheme.

### Claim 10

A method of fabricating an interconnect structure for a semiconductor die, the method comprising:
forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate;
forming an inter-layer dielectric layer above the metallization layer;
forming a first grating hardmask layer above the inter-layer dielectric layer, the first grating hardmask layer having a direction orthogonal to the direction of the alternating metal lines and dielectric lines of the lower metallization layer;
transferring a pattern of the first grating hardmask layer to the inter-layer dielectric layer to form a patterned inter-layer dielectric layer having line regions therein;
forming a pattern accumulation layer above the first grating hardmask layer;
forming a second grating hardmask layer above the pattern accumulation layer, the second grating hardmask layer having a direction parallel with the direction of the alternating metal lines and dielectric lines of the lower metallization layer;
with the second grating hardmask layer in place, transferring a first via pattern to the pattern accumulation layer;
removing the second grating hardmask layer;
subsequent to removing the second grating hardmask layer, transferring a second via pattern to the pattern accumulation layer to form a twice patterned memory layer having a pattern;
transferring the pattern of the twice patterned memory layer to the patterned inter-layer dielectric layer to form a twice patterned inter-layer dielectric layer having via locations therein; and
forming metal vias and metal lines in the via locations and line regions, respectively, of the twice patterned inter-layer dielectric layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
prior to forming the inter-layer dielectric layer, forming a hardmask layer on the lower metallization layer, wherein the inter-layer dielectric layer is formed on the hardmask layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein transferring the pattern of the twice patterned memory layer to the patterned inter-layer dielectric layer further comprises transferring the pattern of the twice patterned memory layer to the hardmask layer.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
subsequent to transferring the pattern of the first grating hardmask layer to the inter-layer dielectric layer, forming a second hardmask layer on the first grating hardmask layer and on the patterned inter-layer dielectric layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein transferring the pattern of the twice patterned memory layer to the patterned inter-layer dielectric layer further comprises transferring the pattern of the twice patterned memory layer to the second hardmask layer.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
forming an etch stop layer on the second hardmask layer, wherein the pattern accumulation layer is formed on the etch stop layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein transferring the pattern of the twice patterned memory layer to the patterned inter-layer dielectric layer further comprises transferring the pattern of the twice patterned memory layer to the etch stop layer.

### Claim 17 (depends on 10)

The method of claim 10, wherein transferring the first and second via patterns to the pattern accumulation layer comprises forming via areas larger than areas of the via locations formed in the inter-layer dielectric layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein transferring the pattern of the twice patterned memory layer to the patterned inter-layer dielectric layer is performed using an etch process that is blocked by exposed portions of the first grating hardmask layer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
subsequent to forming the twice patterned inter-layer dielectric layer and prior to forming the metal vias and metal lines in the via locations and line regions, removing the first grating hardmask layer.

### Claim 20 (depends on 10)

The method of claim 10, wherein forming the first grating hardmask layer comprises using a pitch division processing scheme.