# US 10,319,600 B1 · Thermal silicon etch

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- Number: US 10,319,600 B1
- Document ID: US10319600B1
- Status: Granted
- Kind: B1
- Application number: 15/918,860
- Filed: 2018-03-12
- Granted: 2019-06-11
- Earliest claimed: 2018-03-12
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Zihui Li; Rui Cheng; Anchuan Wang; Nitin K. Ingle; Abhijit Basu Mallick
- Web page: https://patentgrep.com/patent/US10319600B1

## CPC

- H10P 50/242: {of Group IV materials}
- H01J 37/00: Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof (H01J33/00, H01J40/00, H01J41/00, H01J47/00, H01J49/00 take precedence)
- H01J 37/32357: {Generation remote from the workpiece, e.g. down-stream}
- H01J 37/32422: {Arrangement for selecting ions or species in the plasma}
- H01J 37/3244: {Gas supply means}
- H01J 37/32724: {Temperature}
- H10P 50/268: {of silicon-containing layers}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Exemplary methods for selectively removing silicon (e.g. polysilicon) from a patterned substrate may include flowing a fluorine-containing precursor into a substrate processing chamber to form plasma effluents. The plasma effluents may remove silicon (e.g. polysilicon, amorphous silicon or single crystal silicon) at significantly higher etch rates compared to exposed silicon oxide, silicon nitride or other dielectrics on the substrate. The methods rely on the temperature of the substrate in combination with some conductivity of the surface to catalyze the etch reaction rather than relying on a gas phase source of energy such as a plasma.

## Claims

### Claim 1

An etching method comprising:
flowing a fluorine-containing precursor into a substrate processing region of a semiconductor processing chamber, wherein a substrate is positioned within the substrate processing region and the substrate comprises silicon and dielectric, wherein the silicon and the dielectric are exposed on sidewalls of a trench formed in stacked alternating layers of the silicon and the dielectric; and
removing silicon from the sidewalls of the trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein removing silicon from the sidewalls of the trench comprises laterally etching silicon from the sidewalls of the trench.

### Claim 3 (depends on 1)

The method of claim 1, wherein the dielectric is one of silicon oxide or silicon nitride.

### Claim 4 (depends on 1)

The method of claim 1, wherein the silicon comprises one of amorphous silicon, single crystal silicon or polysilicon.

### Claim 5 (depends on 1)

The method of claim 1, wherein the removal of the silicon removes silicon with a horizontal etch progression.

### Claim 6 (depends on 1)

The method of claim 1, wherein the removal of the silicon removes silicon at an etch rate more than twenty times faster than dielectric.

### Claim 7 (depends on 1)

The method of claim 1, wherein the removal of the silicon is performed at a substrate temperature of less than 500° C.

### Claim 8 (depends on 1)

The method of claim 1, wherein the removal of the silicon is performed at a partial pressure of fluorine-containing precursor which is more than 1 Torr.

### Claim 9 (depends on 1)

The method of claim 1, wherein the stacked alternating layers comprise at least 50 layers of alternating layers of the silicon and the dielectric.

### Claim 10 (depends on 1)

The method of claim 1, wherein the trench has an aspect ratio of greater than or about 50:1.

### Claim 11 (depends on 1)

The method of claim 1, wherein a layer of the silicon at an upper region of the trench and a layer of silicon at a lower region of the trench differ in lateral etch amounts by less than about 2 nm.

### Claim 12 (depends on 1)

The method of claim 1, wherein the fluorine-containing precursor is one of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride, hydrogen fluoride, or xenon difluoride.

### Claim 13

An etching method comprising:
flowing a fluorine-containing precursor into a substrate processing region of a semiconductor processing chamber, wherein a substrate is positioned within the substrate processing region and the substrate comprises polysilicon and dielectric, wherein the polysilicon and the dielectric are exposed on sidewalls of a trench formed in stacked alternating layers of the polysilicon and the dielectric; and
laterally etching the polysilicon from the sidewalls of the trench.

### Claim 14 (depends on 13)

The method of claim 13, wherein the lateral removal of polysilicon removes polysilicon with a horizontal etch progression.

### Claim 15 (depends on 13)

The method of claim 13, wherein the lateral removal of polysilicon removes polysilicon at an etch rate more than twenty times faster than the dielectric.

### Claim 16 (depends on 13)

The method of claim 13, wherein the lateral removal of polysilicon is performed at a temperature of less than 600° C.

### Claim 17 (depends on 13)

The method of claim 13, wherein the lateral removal of polysilicon is performed at a partial pressure of fluorine-containing precursor within the substrate processing region which is more than 1 Torr.

### Claim 18 (depends on 13)

The method of claim 13, wherein the trench is characterized by an aspect ratio of greater than or about 50:1.

### Claim 19 (depends on 13)

The method of claim 13, wherein the stacked alternating layers comprise at least 50 layers of alternating layers of the polysilicon and the dielectric.

### Claim 20 (depends on 13)

The method of claim 13, wherein a layer of the polysilicon at an upper region of the trench and a layer of silicon at a lower region of the trench differ in lateral etch amounts by less than about 2 nm.