# US 10,319,596 B2 · Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,596 B2 - Document ID: US10319596B2 - Status: Granted - Kind: B2 - Application number: 15/620,197 - Filed: 2017-06-12 - Published: 2017-09-28 - Granted: 2019-06-11 - Earliest claimed: 2015-10-12 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Takashi Ando; Mohit Bajaj; Terence B. Hook; Rajan K. Pandey; Rajesh Sathiyanarayanan - Web page: https://patentgrep.com/patent/US10319596B2 ## CPC - H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor} - H10D 30/021: {of FETs having insulated gates [IGFET]} - H10D 30/751: {having composition variations in the channel regions} - H10D 30/792: {comprising applied insulating layers, e.g. stress liners} - H10D 30/798: {being provided in or under the channel regions} - H10D 64/01338: {with a treatment, e.g. annealing, after the formation of the conductor} - H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 64/681: {having a compositional variation, e.g. multilayered} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D 84/0144: {Manufacturing their gate insulating layers} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties} - H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz} - H10P 30/40: into insulating materials - H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase - H10P 32/20: Diffusion for doping of insulating layers - H10P 95/90: Thermal treatments, e.g. annealing or sintering - H10D 30/62: Fin field-effect transistors [FinFET] - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed. ## Claims ### Claim 1 A method for adjusting a threshold voltage, comprising: depositing a strained silicon nitride liner on a gate structure to strain a gate dielectric; and adjusting threshold voltage of a transistor by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse from the silicon nitride liner into the gate dielectric in a channel region. ### Claim 2 (depends on 1) The method as recited in claim 1, wherein controlling the strain by one or more of: deposition temperature or liner thickness. ### Claim 3 (depends on 1) The method as recited in claim 1, wherein the gate dielectric includes a high-k dielectric in which a diffusion length of the WF modulating species is modulated in accordance with the strained liner. ### Claim 4 (depends on 1) The method as recited in claim 1, wherein the WF modulating species include O and/or OH. ### Claim 5 (depends on 1) The method as recited in claim 1, wherein adjusting threshold voltage of the transistor includes adjusting threshold voltages of a plurality of transistors using more than one strained liner such that more than one threshold voltage is programmed across a same device. ### Claim 6 (depends on 1) The method as recited in claim 1, wherein the more than one strained liner, each includes different strain levels to provide different threshold voltages. ### Claim 7 (depends on 6) The method as recited in claim 6 further comprising removing the strained silicon nitride liner. ### Claim 8 A method for adjusting threshold voltage, comprising: producing a strain in gate dielectric layers with silicon nitride liners; and introducing work function (WF) modulating species to the gate dielectric layers and the silicon nitride liners wherein due to the strain in the gate dielectric layers, different amounts of the WF modulating species diffuse to the gate dielectric layers at a channel region, resulting in different threshold voltage values. ### Claim 9 (depends on 8) The method as recited in claim 8, wherein producing the strain in the gate dielectric layers comprises depositing includes depositing two or more silicon nitride liners and controlling the strain by one or more of: deposition temperature or liner thickness. ### Claim 10 (depends on 9) The method as recited in claim 9, wherein the gate dielectric includes a high-k dielectric. ### Claim 11 (depends on 10) The method of claim 10, wherein a diffusion length of the WF modulating species is modulated in accordance with strain in the two or more liners. ### Claim 12 (depends on 11) The method as recited in claim 11, further comprising diffusing the WF modulating species by annealing the two or more liners. ### Claim 13 (depends on 12) The method as recited in claim 12, further comprising implanting the WF modulating species through the two or more liners to diffuse the WF modulating species into the gate dielectric layers. ### Claim 14 (depends on 8) The method as recited in claim 8, wherein the WF modulating species include oxygen. ### Claim 15 (depends on 8) The method as recited in claim 8, wherein the WF modulating species include OH. ### Claim 16 (depends on 10) The method as recited in claim 10, wherein the two or more liners are employed to adjust threshold voltages across a same device wherein the device includes a chip. ### Claim 17 (depends on 16) The method of claim 16, further comprising removing the two or more liners. ### Claim 18 A method for adjusting a threshold voltage, comprising: depositing a strained liner of a metal nitride over a gate dielectric; and adjusting threshold voltage by adjusting an amount of strain in the strained liner to control an amount of work function (WF) modulating species including oxygen, OH, or a combination thereof that diffuse into the gate dielectric from the metal nitride of the strained liner. ### Claim 19 (depends on 1) The method as recited in claim 1, wherein controlling the strain by one or more of: deposition temperature or liner thickness. ### Claim 20 (depends on 1) The method as recited in claim 1, wherein the gate dielectric includes a high-k dielectric in which a diffusion length of the WF modulating species is modulated in accordance with the strained liner.