# US 10,319,462 B2 · Semiconductor device and semiconductor system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,462 B2 - Document ID: US10319462B2 - Status: Granted - Kind: B2 - Application number: 15/257,164 - Filed: 2016-09-06 - Published: 2017-12-28 - Granted: 2019-06-11 - Earliest claimed: 2016-06-23 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Do Yun Lee; Chang Hyun Kim - Web page: https://patentgrep.com/patent/US10319462B2 ## CPC - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 2029/0409: {Online test} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A semiconductor device may include an operation control circuit configured to generate a detection signal based on an internal temperature of the semiconductor device. The semiconductor device may include an error correction circuit configured to output read data as output data with or without performing an error correction operation and with or without performing a scrub operation based on the detection signal. ## Claims ### Claim 1 A semiconductor device comprising: an operation control circuit configured for generating a first signal based on an internal temperature being equal to or higher than a first predetermined temperature; an error correction circuit configured for correcting an error of read data according to a read parity and generating output data based on the error correction control signal; and a memory array configured to output the read data and the read parity to the error correction circuit based on a read operation, wherein the operation control circuit is configured to generate a second signal based on the internal temperature being equal to or higher than a second predetermined temperature, wherein the first predetermined temperature is different from the second predetermined temperature, wherein the operation control circuit comprises a temperature sensor, and wherein the temperature sensor generates the first detection signal which is enabled, based on the internal temperature being lower than the first predetermined temperature, generates the second detection signal which is enabled, based on the internal temperature being equal to or higher than the first predetermined temperature and being lower than the second predetermined temperature, and generates the third detection signal which is enabled, based on the internal temperature being equal to or higher than the second predetermined temperature. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first signal includes an error correction control signal and the second signal includes the error correction control signal and a scrub control signal. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the second predetermined temperature is set to be higher than the first predetermined temperature. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein the error correction circuit generates a scrub write control signal and generates scrub data by buffering the output data, based on the scrub control signal. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein the operation control circuit comprises: a control signal generation circuit configured for generating the error correction control signal and the scrub control signal based on the first to third detection signals. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the temperature sensor generates the first detection signal which is enabled, based on the internal temperature being lower than the first predetermined temperature, generates the second detection signal which is enabled, based on the internal temperature being equal to or higher than the first predetermined temperature and being lower than the second predetermined temperature, and generates the third detection signal which is enabled, based on the internal temperature being equal to or higher than the second predetermined temperature. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein the control signal generation circuit generates the error correction control signal based on the second detection signal being enabled, and generates the error correction control signal and the scrub control signal based on the third detection signal being enabled. ### Claim 8 (depends on 2) The semiconductor device according to claim 2, wherein the error correction circuit comprises: a data error correction circuit configured for correcting an error of the read data according to the read parity and outputting the output data, based on the error correction control signal; and a scrub operation control circuit configured for generating the scrub write control signal and generating the scrub data by buffering the output data, based on the scrub control signal. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, further comprising: a read write control circuit configured for generating a read control signal or a write control signal by decoding a command or generating a write control signal based on the scrub write control signal; and a memory core circuit including the memory array, and configured for outputting the read data and the read parity from the memory array based on the read control signal and storing the scrub data in the memory array based on the write control signal. ### Claim 10 A semiconductor device comprising: an operation control circuit configured for generating a first signal based on a level of a core voltage being lower than a level of a reference voltage; and an error correction circuit configured for correcting an error of read data according to a read parity and generating output data based on the first signal; and a memory array configured to output the read data and the read parity to the error correction circuit based on a read operation, wherein the operation control circuit is configured to generate a second signal based on the level of the core voltage being lower than a level obtained by subtracting a level of a predetermined voltage from the level of the reference voltage, wherein the operation control circuit comprises a voltage detection circuit, and wherein the voltage detection circuit generates the first detection signal which is enabled, based on the level of the core voltage being equal to or higher than the level of the reference voltage, generates the second detection signal which is enabled, based on the level of the core voltage being lower than the level of the reference voltage and being equal to or higher than the level obtained by subtracting the level of the predetermined voltage from the level of the reference voltage, and generates the third detection signal which is enabled, based on the level of the core voltage being lower than the level obtained by subtracting the level of the predetermined voltage from the level of the reference voltage. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the first signal includes an error correction control signal and the second signal includes the error correction control signal and a scrub control signal. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the error correction circuit generates a scrub write control signal and generates scrub data by buffering the output data, based on the scrub control signal. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, wherein the operation control circuit comprises: a control signal generation circuit configured for generating the error correction control signal and the scrub control signal based on the first to third detection signals. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the control signal generation circuit generates the error correction control signal based on the second detection signal being enabled, and generates the error correction control signal and the scrub control signal based on the third detection signal being enabled. ### Claim 15 (depends on 10) The semiconductor device according to claim 10, further comprising: a read write control circuit configured for generating a read control signal or a write control signal by decoding a command or generating a write control signal based on the scrub write control signal; and a memory core circuit including the memory array, and configured for outputting the read data and the read parity from the memory array based on the read control signal and storing the scrub data in the memory array based on the write control signal. ### Claim 16 A semiconductor system comprising: a first semiconductor device configured for outputting a command and being inputted with output data; and a second semiconductor device configured for generating a first signal and a second signal depending upon an internal temperature or a level of a core voltage, and generating the output data by correcting an error of read data according to a read parity based on the first signal, based on a read operation being performed based on the command, wherein the read parity and the read data are outputted from a memory array, included in the second semiconductor device, in the read operation, wherein the second semiconductor device is configured to generate the first signal based on the internal temperature being equal to or higher than a first predetermined temperature and to generate the second signal based on the internal temperature being equal to or higher than a second predetermined temperature, wherein the first predetermined temperature is different from the second predetermined temperature, wherein the second semiconductor device comprises a temperature sensor, and wherein the temperature sensor generates the first detection signal which is enabled, based on the internal temperature being lower than the first predetermined temperature, generates the second detection signal which is enabled, based on the internal temperature being equal to or higher than the first predetermined temperature and being lower than the second predetermined temperature, and generates the third detection signal which is enabled, based on the internal temperature being equal to or higher than the second predetermined temperature. ### Claim 17 (depends on 16) The semiconductor system according to claim 16, wherein the first signal includes an error correction control signal and the second signal includes the error correction control signal and a scrub control signal, and wherein the second predetermined temperature is set to be higher than the first predetermined temperature. ### Claim 18 (depends on 17) The semiconductor system according to claim 17, wherein the second semiconductor device generates the error correction control signal based on the level of the core voltage being lower than a level of a reference voltage, and generates the scrub control signal based on the level of the core voltage being lower than a level obtained by subtracting a level of a predetermined voltage from the level of the reference voltage. ### Claim 19 (depends on 16) The semiconductor system according to claim 16, wherein the second semiconductor device generates scrub data by buffering the output data based on the scrub control signal, and stores the scrub data in the memory array. ### Claim 20 A semiconductor device comprising: an operation control circuit configured to generate a first to third detection signals based on an internal temperature of the semiconductor device; and an error correction circuit configured to output read data as output data with or without performing an error correction operation and with or without performing a scrub operation based on the first to third detection signals, wherein the operation control circuit is configured to generate the second detection signal based on the internal temperature being equal to or higher than a first predetermined temperature and to generate the third detection signal based on the internal temperature being equal to or higher than a second predetermined temperature, and wherein the first predetermined temperature is different from the second predetermined temperature. ### Claim 21 (depends on 20) The semiconductor device according to claim 20, wherein when the internal temperature is below the first predetermined temperature the error correction circuit is configured to output the read data as the output data without performing the error correction operation and without performing the scrub operation. ### Claim 22 (depends on 20) The semiconductor device according to claim 20, wherein when the internal temperature is greater than or equal to a first predetermined temperature and less than the second predetermined temperature the error correction circuit is configured to output the read data as the output data with performing the error correction operation and without performing the scrub operation, and wherein the second predetermined temperature is set to be greater than the first predetermined temperature. ### Claim 23 (depends on 20) The semiconductor device according to claim 20, wherein when the internal temperature is greater than a first and a second predetermined temperature the error correction circuit is configured to output the read data as the output data with performing the error correction operation and with performing the scrub operation, and wherein the second predetermined temperature is set to be greater than the first predetermined temperature. ### Claim 24 (depends on 20) The semiconductor device according to claim 20, wherein the error correction operation includes correcting an error of the read data according to a read parity and generating the output data, and wherein the scrub operation includes generating scrub data by buffering the output data. ### Claim 25 A semiconductor device comprising: an operation control circuit configured to generate a first to third detection signals based on a level of a core voltage of the semiconductor device; and an error correction circuit configured to output read data as output data with or without performing an error correction operation and with or without performing a scrub operation based on the first to third detection signals, wherein the operation control circuit is configured to generate the second detection signal based on a level of a core voltage being lower than a level of a reference voltage and to generate the third detection signal based on the level of the core voltage being lower than a level obtained by subtracting a level of a predetermined voltage from the level of the reference voltage. ### Claim 26 (depends on 25) The semiconductor device according to claim 25, wherein when the level of the core voltage is equal to or higher than the reference voltage the error correction circuit is configured to output the read data as the output data without performing the error correction operation and without performing the scrub operation. ### Claim 27 (depends on 25) The semiconductor device according to claim 25, wherein when the level of the core voltage is lower, by a level equal to or lower than the level of the predetermined voltage, than the reference voltage the error correction circuit is configured to output the read data as the output data with performing the error correction operation and without performing the scrub operation. ### Claim 28 (depends on 25) The semiconductor device according to claim 25, wherein when the level of the core voltage is lower, by a level higher than the level of the predetermined voltage, than the reference voltage the error correction circuit is configured to output the read data as the output data with performing the error correction operation and with performing the scrub operation. ### Claim 29 (depends on 25) The semiconductor device according to claim 25, wherein the error correction operation includes correcting an error of the read data according to a read parity and generating the output data, and wherein the scrub operation includes generating scrub data by buffering the output data.