# US 10,319,458 B2 · Hardware apparatuses and methods to check data storage devices for transient faults > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,458 B2 - Document ID: US10319458B2 - Status: Granted - Kind: B2 - Application number: 15/457,326 - Filed: 2017-03-13 - Published: 2017-06-29 - Granted: 2019-06-11 - Earliest claimed: 2015-06-25 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Ashok Raj; Ron Gabor; Hisham Shafi; Mohan J. Kumar; Theodros Yigzaw - Web page: https://patentgrep.com/patent/US10319458B2 ## CPC - G11C 29/38: Response verification devices - G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 2029/0401: {in embedded memories} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor. ## Claims ### Claim 1 A processor comprising: a decoder to decode an instruction, having a first operand to identify a section of a data storage device, into a decoded instruction; and an execution unit to execute the decoded instruction to: perform a check of the section of the data storage device for a memory fault that is to cause a machine check exception that shuts down the processor when data is accessed by the processor at the section, and provide as a resultant of the instruction an indication of failure when there is the memory fault without causing the machine check exception, and an indication of success when there is not the memory fault. ### Claim 2 (depends on 1) The processor of claim 1, wherein the instruction comprises a second operand to indicate a length of the section of the data storage device, and the first operand is to indicate a starting virtual address of the section of the data storage device. ### Claim 3 (depends on 1) The processor of claim 1, wherein the indication of failure is an offset, from a starting virtual address of the section of the data storage device, where the memory fault occurred. ### Claim 4 (depends on 1) The processor of claim 1, wherein the indication of failure is an address where the memory fault occurred. ### Claim 5 (depends on 4) The processor of claim 4, wherein the address is a virtual address. ### Claim 6 (depends on 1) The processor of claim 1, wherein the execution unit is to execute the decoded instruction to further: check that the section of the data storage device has a starting address that is cache line aligned. ### Claim 7 (depends on 1) The processor of claim 1, wherein the execution unit is to execute the decoded instruction to further: check that a length of the section is a multiple of a cache line size of the data storage device. ### Claim 8 (depends on 1) The processor of claim 1, wherein the execution unit is to execute the decoded instruction to write the resultant to a register. ### Claim 9 A method comprising: decoding an instruction, having a first operand to identify a section of a data storage device, into a decoded instruction with a decoder of a processor; and executing the decoded instruction with an execution unit of the processor to: perform a check of the section of the data storage device for a memory fault that is to cause a machine check exception that shuts down the processor when data is accessed by the processor at the section, and provide as a resultant of the instruction an indication of failure when there is the memory fault without causing the machine check exception, and an indication of success when there is not the memory fault. ### Claim 10 (depends on 9) The method of claim 9, wherein the instruction comprises a second operand indicating a length of the section of the data storage device, and the first operand indicates a starting virtual address of the section of the data storage device. ### Claim 11 (depends on 9) The method of claim 9, wherein the indication of failure is an offset, from a starting virtual address of the section of the data storage device, where the memory fault occurred. ### Claim 12 (depends on 9) The method of claim 9, wherein the indication of failure is an address where the memory fault occurred. ### Claim 13 (depends on 12) The method of claim 12, wherein the address is a virtual address. ### Claim 14 (depends on 9) The method of claim 9, wherein the executing the decoded instruction with the execution unit of the processor is to further: check that the section of the data storage device has a starting address that is cache line aligned. ### Claim 15 (depends on 9) The method of claim 9, wherein the executing the decoded instruction with the execution unit of the processor is to further: check that a length of the section is a multiple of a cache line size of the data storage device. ### Claim 16 (depends on 9) The method of claim 9, wherein the executing the decoded instruction with the execution unit of the processor is to write the resultant to a register. ### Claim 17 A non-transitory machine readable storage medium having code that, when executed, causes a machine to perform a method comprising: decoding an instruction, having a first operand to identify a section of a data storage device, into a decoded instruction with a decoder of a processor; and executing the decoded instruction with an execution unit of the processor to: perform a check of the section of the data storage device for a memory fault that is to cause a machine check exception that shuts down the processor when data is accessed by the processor at the section, and provide as a resultant of the instruction an indication of failure when there is the memory fault without causing the machine check exception, and an indication of success when there is not the memory fault. ### Claim 18 (depends on 17) The non-transitory machine readable storage medium of claim 17, wherein the instruction comprises a second operand indicating a length of the section of the data storage device, and the first operand indicates a starting virtual address of the section of the data storage device. ### Claim 19 (depends on 17) The non-transitory machine readable storage medium of claim 17, wherein the indication of failure is an offset, from a starting virtual address of the section of the data storage device, where the memory fault occurred. ### Claim 20 (depends on 17) The non-transitory machine readable storage medium of claim 17, wherein the indication of failure is an address where the memory fault occurred. ### Claim 21 (depends on 20) The non-transitory machine readable storage medium of claim 20, wherein the address is a virtual address. ### Claim 22 (depends on 17) The non-transitory machine readable storage medium of claim 17, wherein the executing the decoded instruction with the execution unit of the processor is to further: check that the section of the data storage device has a starting address that is cache line aligned. ### Claim 23 (depends on 17) The non-transitory machine readable storage medium of claim 17, wherein the executing the decoded instruction with the execution unit of the processor is to further: check that a length of the section is a multiple of a cache line size of the data storage device. ### Claim 24 (depends on 17) The non-transitory machine readable storage medium of claim 17, wherein the executing the decoded instruction with the execution unit of the processor is to write the resultant to a register.