# US 10,319,456 B2 · Apparatus and method for measuring performance of memory array

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- Number: US 10,319,456 B2
- Document ID: US10319456B2
- Status: Granted
- Kind: B2
- Application number: 15/879,455
- Filed: 2018-01-25
- Published: 2019-02-28
- Granted: 2019-06-11
- Earliest claimed: 2017-08-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chi-Hsu Chiu; Shih-Feng Huang; Yi-Sin Wang; Arjit Ashok
- Web page: https://patentgrep.com/patent/US10319456B2

## CPC

- G11C 29/14: Implementation of control logic, e.g. test mode decoders
- G01R 31/2601: {Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence)}
- G01R 31/275: {for testing individual semiconductor components within integrated circuits}
- G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]}
- G11C 29/021: {in voltage or current generators}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details}
- G11C 29/38: Response verification devices
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 2029/0403: {during or with feedback to manufacture}
- G11C 2029/1206: {Location of test circuitry on chip or wafer}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

The disclosure is related a method for testing and measuring the performances of electrical components on a semiconductor IC device through a test apparatus (also referred to as a testline) disposed in a scribe line between the semiconductor IC devices on a wafer. The test apparatus may include a built-in self-test (BIST) circuit and a duplication of the electrical components subjected to the performance measurement. Minimum and maximum testing voltages are provided to the test apparatus, where the range of voltage between the minimum and maximum testing voltages are divided into a plurality of testing operational voltages which are applied to the test apparatus. For each testing operational voltages, a memory array operation test is performed, where at least one of the testing operational voltages resulting in a performance failure is identified as the minimal operating voltage of the memory array.

## Claims

### Claim 1

A method for detecting minimal operation voltage of memory array, comprising:
receiving a minimum testing voltage and a maximum testing voltage;
dividing a range of voltage between the minimum testing voltage and the maximum testing voltage into a plurality of testing voltages;
performing a memory array operation test on the memory array for each of the testing voltages, wherein the testing voltages are provided for operating the memory array;
detecting an occurrence of failure in the memory array in a failure memory array operation test; and
detecting at least one of the testing voltages utilized for operating the memory array during the detected failure memory array operation test.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
outputting the testing voltage utilized for operating the memory array during the detected failure memory array operation test as the minimal operation voltage of the memory array.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
delaying for a predetermined number of cycles before performing each SRAM performance test.

### Claim 4 (depends on 1)

The method of claim 1, wherein the memory array operation test comprises:
writing a first data pattern to the memory array;
reading a second data pattern to the memory array;
comparing the second data pattern to the first data pattern; and
determining that a failure has occurred in the memory array when the second data pattern and the first data pattern does not match.

### Claim 5 (depends on 4)

The method of claim 4, wherein the memory array operation test further comprises:
recording at least one of the testing voltages utilized for operating the memory array during the detected failure memory array operation test.

### Claim 6 (depends on 4)

The method of claim 4, wherein the memory array operation test further comprises:
delaying the writing of first data pattern to the memory array as to compensate a signal delay generated by propagation of a signal through a long and narrow structure.

### Claim 7

A method of measuring an operation of a memory array, comprising:
applying a plurality of testing operational voltages to the memory array;
for each of the testing operational voltages,
performing a writing operation to write an expected data pattern to the memory array;
performing a reading operation to the memory array to obtain a read data pattern; and
performing a comparing operation to compare the read data pattern to the expected data pattern for determining a performance failure.

### Claim 8 (depends on 7)

The method of claim 7, comprising:
recording at least one of the operational testing voltages at which the performance failure was detected.

### Claim 9 (depends on 7)

The method of claim 7, comprising:
outputting the at least one of the operational testing voltages at which the performance failure was detected as a minimal operating voltage of the memory array.

### Claim 10 (depends on 9)

The method of claim 9, wherein the outputted operational testing voltage is the first operational testing voltage at which the performance failure is detected.

### Claim 11 (depends on 7)

The method of claim 7, comprising:
delaying the writing operation to the memory array as to compensate a signal delay generated by propagation of a signal through a long and narrow structure.

### Claim 12

A test apparatus, disposed in a scribe line of wafer, comprising:
a first test pad, receiving a minimum testing voltage;
a second test pad, receiving a maximum testing voltage
a memory array;
a built-in self-test (BIST) circuit, electrically connected to the test pads and the memory array, dividing a range of voltage between the minimum testing voltage and the maximum testing voltage into a plurality of testing voltages, and programmed to perform the following steps:
respectively performing a memory array operation test on the memory array for each of the testing voltages, wherein the testing voltages are provided for operating the memory array;
detecting an occurrence of a failure in the memory array in a failure memory array operation test; and
outputting the testing voltage corresponding to the failure memory array operation test as a minimal operation voltage of the memory array through a third test pad.

### Claim 13 (depends on 12)

The test apparatus of claim 12, further comprises:
a delay circuit, coupled to a clock signal; and
a data storage circuit, coupled between the BIST circuit and the memory array, and configured to receive test data pattern from the BIST circuit and output the test data pattern to the memory array based on the output of the delay circuit.

### Claim 14 (depends on 12)

The test apparatus of claim 12, wherein the memory array is a duplication of a portion of the memory array disposed in the die area.

### Claim 15 (depends on 12)

The test apparatus of claim 12, further comprising
a counter, counting cycles of a clock signal,
wherein the BIST circuit is programmed to delay for a predetermined number of cycles before performing each memory array operation test.

### Claim 16 (depends on 12)

The test apparatus of claim 12, wherein the BIST circuit further comprises a voltage divider, sequentially outputting one of the testing voltages to operate the memory array.

### Claim 17 (depends on 16)

The test apparatus of claim 16, wherein the voltage divider comprises:
a plurality of resistors, connected in series, wherein one terminal of the serially connected resistors is electrically connected to the first test pad, and another terminal the serial connected resistors is electrically connected to the second test pad; and
a plurality of transistors, wherein each transistor is electrically connected between an intersection of two resistors and an output terminal of the voltage divider, and controlled by the BIST circuit to divide the range of voltage between the minimum and maximum testing voltages in to N number of testing voltages.

### Claim 18 (depends on 12)

The test apparatus of claim 12, where the test apparatus is a long and narrow structure.

### Claim 19 (depends on 12)

The test apparatus of claim 12, wherein, in the memory array operation test for each testing voltage, the BIST circuit is programmed to perform the following steps:
applying a plurality of testing operational voltages to the memory array;
for each of the testing operational voltages,
performing a writing operation to write an expected data pattern to the memory array;
performing a reading operation to the memory array to obtain a read data pattern; and
performing a comparing operation to compare the read data pattern to the expected data pattern for determining at least one of the testing voltages for which the failure operation test is detected.

### Claim 20 (depends on 19)

The test apparatus of claim 19, wherein the BIST circuit is further programmed to delay the reading operation to the memory array after the writing operation for a predetermined period of time.