# US 10,319,455 B2 · Semiconductor device

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- Number: US 10,319,455 B2
- Document ID: US10319455B2
- Status: Granted
- Kind: B2
- Application number: 15/641,098
- Filed: 2017-07-03
- Published: 2018-07-05
- Granted: 2019-06-11
- Earliest claimed: 2017-01-04
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Yong Mi Kim; Jae Il Kim
- Web page: https://patentgrep.com/patent/US10319455B2

## CPC

- G11C 29/1201: {comprising I/O circuitry}
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/1009: {Data masking during input/output}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2207/2272: Latency related aspects
- G11C 2207/2281: Timing of a read operation
- G11C 2207/229: Timing of a write operation
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.

## Claims

### Claim 1

A semiconductor device comprising:
a delay selection signal generation circuit configured to generate a delay selection signal in response to an information code signal;
an internal read signal generation circuit configured to generate an internal read signal according to a mask write signal, the delay selection signal, and a clock signal; and
an internal write signal generation circuit configured to delay the mask write signal by a predetermined delay period to generate an internal write signal.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the information code signal is stored internally through a mode register set operation.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the internal read signal generation circuit delays the mask write signal by a delay period in synchronization with the clock signal to generate the internal read signal, the delay period being determined according to a combination of logic values of the information code signal.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the delay selection signal comprises first and second delay selection signals, and
wherein the first and second delay selection signals are selectively enabled in accordance with a logic value of the information code signal.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the internal read signal generation circuit includes:
a delay signal generation circuit configured to sequentially delay the mask write signal in synchronization with the clock signal to generate a first delay signal and a second delay signal.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the delay signal generation circuit includes:
a first delay circuit configured to delay the mask write signal in synchronization with the clock signal to generate the first delay signal; and
a second delay circuit configured to delay the first delay signal in synchronization with the clock signal to generate the second delay signal.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein the internal read signal generation circuit further includes:
a delay signal selection circuit configured to generate the internal read signal from the first and second delay signals in response to the first and second delay selection signals.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the delay signal selection circuit outputs the first delay signal as the internal read signal when the first delay selection signal is enabled, and outputs the second delay signal as the internal read signal when the second delay selection signal is enabled.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the predetermined delay period is determined to enable the internal write signal after the correction data is generated.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the data correction circuit replaces some bits of the input data with read data and generates the correction data using an error correction code.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, further comprising a command decoder configured to decode an external control signal and generate the mask write signal,
wherein the mask write signal is enabled to initiate a mask write operation in which some bits of input data are written in a masked state.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the external control signal includes one or both of a command and an address.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a data storage circuit configured to output data stored in a memory cell array in response to the internal read signal, and stores correction data in the memory cell array in response to the internal write signal.

### Claim 14

A semiconductor device comprising:
an internal read signal generation circuit configured to delay a mask write signal by a first delay period in response to a delay selection signal to generate an internal read signal, the delay selection signal being generated according to an information code signal;
an internal write signal generation circuit configured to delay the mask write signal by a second delay period to generate an internal write signal; and
a data storage circuit configured to output data stored in a memory cell array in response to the internal read signal, and store correction data in the memory cell array in response to the internal write signal.

### Claim 15 (depends on 14)

The semiconductor device according to claim 14, wherein the information code signal includes a plurality of information code signals, and
wherein the internal read signal generation circuit delays the mask write signal in synchronization with a clock signal according to a combination of logic values of the plurality of information code signals.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the information code signal is stored internally through a mode register set operation.

### Claim 17 (depends on 14)

The semiconductor device according to claim 14, wherein the delay selection signal includes first and second delay selection signals, and
wherein the internal read signal generation circuit includes:
a delay signal generation circuit configured to sequentially delay the mask write signal in synchronization with a clock signal to generate a first delay signal and a second delay signal; and
a delay signal selection circuit configured to select one of the first and second delay signals as the internal read signal in response to the first and second delay selection signals.

### Claim 18 (depends on 14)

The semiconductor device according to claim 14, wherein the second delay period is determined to enable the internal write signal after the correction data is generated.

### Claim 19 (depends on 18)

The semiconductor device according to claim 18, wherein the data correction circuit replaces some bits of the input data with read data and generates the correction data using an error correction code, the read data being the data output from the memory cell array.

### Claim 20 (depends on 14)

The semiconductor device according to claim 14, further comprising a command decoder configured to decode an external control signal and generate the mask write signal,
wherein the mask write signal is enabled to initiate a mask write operation in which some bits of input data are written in a masked state.