# US 10,319,446 B2 · Semiconductor memory device

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- Number: US 10,319,446 B2
- Document ID: US10319446B2
- Status: Granted
- Kind: B2
- Application number: 15/398,229
- Filed: 2017-01-04
- Published: 2018-01-11
- Granted: 2019-06-11
- Earliest claimed: 2016-07-11
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Won Sun Park
- Web page: https://patentgrep.com/patent/US10319446B2

## CPC

- G11C 16/12: Programming voltage switching circuits
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/32: Timing circuits
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Provided herein is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks; a voltage generation circuit configured to generate a plurality of operating voltages; a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted; and a control logic configured to generate the data signal, internal address signals and an internal clock signal in response to a command.

## Claims

### Claim 1

A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a voltage generation circuit configured to generate a plurality of operating voltages;
a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted; and
a control logic configured to generate the data signal, parallel internal address signals and an internal clock signal in response to a command.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1,, wherein the control logic is configured to generate parallel N-bit encoding signals in response to the command, convert the N-bit encoding signals into the data signal, and generate the internal address signals and the internal clock signal herein N is a natural number.

### Claim 3 (depends on 2)

The semiconductor memory device according to claim 2, wherein the total number of bits of the data signal, the internal address signals and the internal clock signal is less than “N”.

### Claim 4

The semiconductor memory device according to claim, wherein the control logic comprises:
a microcontroller configured to selectively output a plurality of operation phase codes according to sub-operations forming the operation in response to the command;
an encoding signal generation circuit configured to generate parallel N-bit encoding signals in response to the plurality of operation phase codes; and
a sequential output circuit configured to convert the N-bit encoding signals into the data signal.

### Claim 5 (depends on 4)

The semiconductor memory device according to claim 4, wherein the microcontroller is configured to output a reset signal in an initial operation phase among the operation phases, and generate a synchronization signal'that toggles in the other phases among the operation phases.

### Claim 6 (depends on 5)

The semiconductor memory device according to claim 5, wherein the decoder circuit comprises:
a prefetch register configured to convert the data signal into parallel internal data signals according to the internal address signals;
an output register configured to restore the N-bit encoding signals from the internal data signals in response to the synchronization signal;
a global word line decoder configured to decode the restored N-bit encoding signals into M-bit decoding signals; and
a switching circuit configured to switch the operating voltages to global word line groups in response to the M-bit decoding signals.

### Claim 7 (depends on 6)

The semiconductor memory device according to claim 6, wherein the prefetch register comprises:
a dock signal generation circuit configured to generate an “N” number of clock signals according to the internal address signals and the internal clock signal; and
a register circuit configured to converts the data signal into the internal data signals in response to the “N” number of clock signals.

### Claim 8

The semiconductor memory device according to claim
wherein the register circuit comprises an “N” number of registers, and
wherein each of the “N” number of registers is configured to output corresponding one of the internal data signals in response to corresponding one among the “N” number of clock signals.

### Claim 9 (depends on 6)

The semiconductor memory device according to claim 6, wherein the prefetch register is configured to store in advance the data signal corresponding to a next operation phase during a current operation phase among the operation phases.

### Claim 10 (depends on 6)

The semiconductor memory device according to claim 6,
wherein the output register comprises an “N” number of registers, and
wherein the “N” number of registers transfers the internal data signals as the restored N-bit encoding signals, respectively, from the prefetch register to the global word line decoder.

### Claim 11

A semiconductor memory device comprising:
a control logic configured to generate parallel N-bit (N is a natural number) encoding signals according to an operation phase code, and to convert the N-bit encoding signals into a serial 1-bit data signal that is serially outputted; and
a decoder circuit configured to restore the N-bit encoding signals from the 1-bit data signal, and then switch a plurality of operating voltages according to the restored N-bit encoding signals.

### Claim 12 (depends on 11)

The semiconductor memory device according to claim 11, wherein the control logic further generates parallel internal address signals and an internal clock signal for the data signal.

### Claim 13 (depends on 12)

The semiconductor memory device according to claim 12, wherein the total number of bits of the data signal, the internal address signals and the internal clock signal is less than “N”.

### Claim 14 (depends on 12)

The semiconductor memory device according to claim 12, wherein the control logic comprises:
a microcontroller configured to selectively output the operation phase code in response to a command;
an encoding signal generation circuit configured to generate the N-bit encoding signals in response to the operation phase code; and
a sequential output circuit, configured to convert the N-bit encoding signals into the data signal, and generate the internal address signals and the internal clock signal.

### Claim 15 (depends on 14)

The semiconductor memory device according to claim 14, wherein the microcontroller is configured to output a reset signal in an initial operation phase among operation phases, and generate a synchronization signal that toggles in the other phases among the operation phases.

### Claim 16 (depends on 15)

The semiconductor memory device according to claim 15, wherein the decoder circuit comprises:
a prefetch register configured to convert the data signal into parallel internal data signals according to the internal address signals;
an output register configured to restore the N-bit encoding signals from the internal data signals in response to the synchronization signal;
a global word line decoder configured to decode the restored N-bit encoding signals into M-bit decoding signals; and
a switching circuit configured to switch the operating voltages to global word line groups in response to the M-bit decoding signals.

### Claim 17 (depends on 16)

The semiconductor memory device according to claim 16, wherein the prefetch register comprises:
a clock signal generation circuit configured to generate an “N” number of dock signals according to the internal address signals and the internal clock signal; and
a register circuit configured to converts the data signal into the internal data signal in response to the “N” number of clock signals.

### Claim 18 (depends on 16)

The semiconductor memory device according to claim 16,
wherein the output register comprises an “N” number of registers, and
wherein the “N” number of registers transfers the internal data signals as the restored N-bit encoding signals, respectively, from the prefetch register to the global word line decoder.

### Claim 19

A semiconductor memory device comprising:
a memory cell array;
a voltage generation circuit configured to generate a plurality of operating voltages;
a control logic configured to generate parallel N-bit encoding signals and parallel-to-serial convert the N-bit encoding signals into a serial 1-bit data signal toggling N times to represent the N-bit encoding signals; and
a decoder circuit configured to transfer one or more of the operating voltages to the memory cell ay in response to the 1-bit data signal.

### Claim 20 (depends on 19)

The semiconductor memory device of claim 19,
wherein the control logic further generates multi-bit internal address signals and a 1-bit internal clock signal, and
wherein the decoder restores the N-bit encoding signals from the 1-bit data according to the multi-bit internal address signals and the 1-bit internal clock signal, decodes the restored N-bit encoding signals into M-bit decoding signals, and transfer the operating voltages to the memory cell array according to the M-bit decoding signals.