# US 10,319,444 B2 · Memory data randomizer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,444 B2 - Document ID: US10319444B2 - Status: Granted - Kind: B2 - Application number: 15/797,002 - Filed: 2017-10-30 - Published: 2019-05-02 - Granted: 2019-06-11 - Earliest claimed: 2017-10-30 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Masatoshi Ishii; Nobuyuki Ohba; Atsuya Okazaki - Web page: https://patentgrep.com/patent/US10319444B2 ## CPC - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G06N 3/063: using electronic means - G06N 3/065: Analogue means - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 8/10: Decoders - G11C 11/54: using elements simulating biological cells, e.g. neuron - G11C 16/10: Programming or data input circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/20: Initialising; Data preset; Chip identification - G11C 27/005: {with non-volatile charge storage, e.g. on floating gate or MNOS} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes selecting each word line through a row decoder connected to all word lines to switch all synaptic NVRAM cells of the selected lines. The method includes driving, on the selected lines, a wave generated by a PLL circuit connected to the row decoder. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines through a column decoder connected to all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells. ## Claims ### Claim 1 A method of initializing a chip having synaptic Non-Volatile Random Access Memory (NVRAM) cells connected row-wise by word lines and column-wise by bit lines, the method comprising: selecting each of the word lines through a row decoder connected to all of the word lines to switch all of the synaptic NVRAM cells of the selected word lines; driving, on the selected word lines, a wave generated by a Phase Locked Loop (PLL) circuit connected to the row decoder; generating standing waves from the wave on the selected word lines by implementing a resonance detection point at an input end of each the word lines; applying a write voltage on all of the bit lines through a column decoder connected to all of the bit lines; and simultaneously driving each of the synaptic NVRAM cells of the selected word lines by different writing currents for different durations in order to set different analog values to all of the synaptic NVRAM cells. ### Claim 2 (depends on 1) The method of claim 1, wherein the chip is a neuromorphic chip. ### Claim 3 (depends on 2) The method of claim 2, wherein the NVRAM cells of the neuromorphic chip are configured to form a synaptic cell array. ### Claim 4 (depends on 1) The method of claim 1, wherein applying a write voltage comprises closing a switch connecting the column decoder to the write voltage. ### Claim 5 (depends on 1) The method of claim 1, further comprising using a respective set of capacitors at the input end of the word lines to provide a random offset to the different analog values on the selected word-lines. ### Claim 6 (depends on 1) The method of claim 1, wherein each of the word lines comprise the input end and an output end, the input end being closest to the row decoder, and the output end being farthest from the row decoder. ### Claim 7 (depends on 1) The method of claim 1, further comprising applying a set of Pulse Width Modulators (PWMs) to the bit lines to further randomize the different writing currents. ### Claim 8 (depends on 1) The method of claim 1, further comprising inputting detected resonance on the resonance detection point on each of the selected word lines to a multiplexer for selectively providing a control signal to the PLL. ### Claim 9 (depends on 1) The method of claim 1, wherein the wave is driven by the PLL on multiple ones of the selected word lines in parallel. ### Claim 10 (depends on 1) The method of claim 1, further comprising adding a bias to the selected word lines. ### Claim 11 A system for initializing a chip having synaptic Non-Volatile Random Access Memory (NVRAM) cells connected row-wise by word lines and column-wise by bit lines, the system comprising: a column decoder connected to all of the bit lines; a row decoder, connected to all of the word lines, for selecting each of the word lines to switch all of the synaptic NVRAM cells of the selected word lines; a Phase Locked Loop (PLL) circuit connected to the row decoder for driving a wave on the selected word lines; a resonance detection point implemented at an input end of each the word lines to generate standing waves from the wave on the selected word lines; and a switch for applying a write voltage on all of the bit lines through the column decoder, wherein each of the synaptic NVRAM cells of the selected word lines is simultaneously driven by different writing currents for different durations in order to set different analog values to all of the synaptic NVRAM cells.