# US 10,319,442 B2 · Parallel-connected merged-floating-gate nFET-pFET EEPROM cell and array

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- Number: US 10,319,442 B2
- Document ID: US10319442B2
- Status: Granted
- Kind: B2
- Application number: 15/955,884
- Filed: 2018-04-18
- Published: 2019-05-02
- Granted: 2019-06-11
- Earliest claimed: 2017-10-31
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Tak Ning; Jeng-Bang Yau
- Web page: https://patentgrep.com/patent/US10319442B2

## CPC

- G11C 16/045: {Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate}
- H10B 41/30: characterised by the memory core region
- H10B 41/40: characterised by the peripheral circuit region
- H10D 30/685: {from the channel}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A shared floating gate device, the device including an nFET, a pFET including a different material than that of the nFET, and a floating gate.

## Claims

### Claim 1

A shared floating gate device, the device comprising:
an nFET;
a pFET comprising a different material than that of the nFET; and
a floating gate.

### Claim 2 (depends on 1)

The device of claim 1, wherein the nFET and the pFET share the floating gate to form an electrically erasable and programmable non-volatile memory device.

### Claim 3 (depends on 1)

The device of claim 1, wherein the nFET includes an nFET gate dielectric,
wherein the pFET includes a pFET gate dielectric, and
wherein the pFET gate dielectric comprises different materials.

### Claim 4 (depends on 3)

The device of claim 3, wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET gate dielectric and the pFET gate dielectric is 1 eV or less.

### Claim 5 (depends on 1)

The device of claim 1, wherein the nFET comprises one of:
Y2O3;
ZrO2; and
HfO2.

### Claim 6 (depends on 1)

The device of claim 1, wherein the pFET comprises one of:
Si3N4;
Y2O3;
ZrO2; and
HfO2.

### Claim 7

An electrically erasable programmable read-only memory (EEPROM) cell, the cell comprising:
an nFET including a source;
a pFET including a drain and comprising a different material than that of the nFET;
a floating gate; and
an nFET access transistor including a drain connected to the source of the nFET and the drain of the pFET.

### Claim 8 (depends on 7)

The cell of claim 7, wherein the nFET and the pFET share the floating gate to form an electrically programmable and erasable non-volatile memory device.

### Claim 9 (depends on 7)

The cell of claim 7, wherein the nFET includes an nFET gate dielectric,
wherein the pFET includes a pFET gate dielectric, and
wherein the pFET gate dielectric comprises different materials.

### Claim 10 (depends on 9)

The cell of claim 9, wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET gate dielectric and pFET gate dielectric is 1 eV or less.

### Claim 11 (depends on 7)

The cell of claim 7, wherein the nFET comprises one of:
Y2O3;
ZrO2; and
HfO2.

### Claim 12 (depends on 7)

The cell of claim 7, wherein the pFET comprises one of:
Si3N4;
Y2O3;
ZrO2; and
HfO2.

### Claim 13

An array structure, comprising:
a plurality of cells, each cell including:
an nFET including a source;
a pFET including a drain and comprising a different material than that of the nFET;
a floating gate; and
an nFET access transistor including a drain connected to the source of the nFET and the drain of the pFET.

### Claim 14 (depends on 13)

The array structure of claim 13, further comprising one nFET access transistor per word-line.

### Claim 15 (depends on 13)

The array structure of claim 13, further comprising one bit-line per pFET access transistor.

### Claim 16 (depends on 13)

The array structure of claim 13, further comprising word-line and two bit-lines per each cell, said word-line being connected to the gate of the access transistor, one of said bit-lines being connected to the source of the pFET and the other one of said bit-lines being connected to the drain of nFET.

### Claim 17 (depends on 13)

The array structure of claim 13, further comprising peripheral logic circuits,
wherein the plurality of cells and the peripheral logic circuits are built on a same substrate.

### Claim 18 (depends on 13)

The array structure of claim 13, further comprising peripheral logic circuits,
wherein the plurality of cells is built on a polycrystalline silicon film-on-insulator and the peripheral logic circuits are built on a bulk silicon substrate.

### Claim 19 (depends on 13)

The array structure of claim 13, further comprising peripheral logic circuits,
wherein the plurality of cells and the peripheral logic circuits are built on a same bulk silicon substrate.