# US 10,319,438 B2 · Memory with margin current addition and related methods

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,438 B2
- Document ID: US10319438B2
- Status: Granted
- Kind: B2
- Application number: 15/797,860
- Filed: 2017-10-30
- Published: 2018-03-08
- Granted: 2019-06-11
- Earliest claimed: 2016-08-02
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMicroelectronics S.r.l.
- Inventors: Emanuela Calvetti; Marcella Carissimi; Marco Pasotti
- Web page: https://patentgrep.com/patent/US10319438B2

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 2013/0042: {Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2013/0066: {Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.

## Claims

### Claim 1

A memory comprising:
a memory element, wherein the memory element comprises a phase change material (PCM) or a first variable resistance, or wherein the memory element is implemented with resistive random-access memory technology (RRAM) or magnetoresistive random-access memory technology (MRAM);
a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current; and
a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.

### Claim 2 (depends on 1)

The memory of claim 1, wherein the memory element comprises a phase change material (PCM).

### Claim 3 (depends on 1)

The memory of claim 1, wherein the memory element comprises a first variable resistance.

### Claim 4 (depends on 1)

The memory of claim 1, wherein the memory element is implemented with resistive random-access memory technology (RRAM).

### Claim 5 (depends on 1)

The memory of claim 1, wherein the memory element is implemented with magnetoresistive random-access memory technology (MRAM).

### Claim 6 (depends on 1)

The memory of claim 1, wherein the margin current branch comprises a control switch coupled to the sense amplifier circuit and configured to control flow of the margin current.

### Claim 7

A memory comprising:
a memory element;
a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current; and
a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current, wherein the margin current branch comprises a control switch coupled to the sense amplifier circuit and configured to control flow of the margin current, and wherein the control switch is configured to perform a logic check operation on the memory element by adding the margin current to the sense current during the sense operation.

### Claim 8

A memory comprising:
a memory element;
a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current;
a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current, wherein the margin current branch comprises a control switch coupled to the sense amplifier circuit and configured to control flow of the margin current; and
a controller configured to flag the memory element with an error value when the sense operation has a different output value when the margin current is added.

### Claim 9 (depends on 1)

The memory of claim 1, wherein the margin current branch comprises a plurality of current sources.

### Claim 10

A memory comprising:
a memory element;
a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current; and
a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current, wherein the margin current branch comprises a control switch coupled to the sense amplifier circuit and configured to control flow of the margin current, and wherein the margin current branch is configured to generate different margin currents.

### Claim 11

A method for making a memory, the method comprising:
forming a memory element, wherein the memory element comprises a phase change material (PCM) or a first variable resistance, or wherein the memory element is implemented with resistive random-access memory technology (RRAM) or magnetoresistive random-access memory technology (MRAM);
forming a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current; and
forming a margin current branch coupled in parallel with the memory element and configured to selectively add a margin current to the sense current.

### Claim 12 (depends on 11)

The method of claim 11, wherein the memory element comprises a phase change material (PCM).

### Claim 13 (depends on 11)

The method of claim 11, wherein the memory element comprises a first variable resistance.

### Claim 14 (depends on 11)

The method of claim 11, wherein the memory element is implemented with resistive random-access memory technology (RRAM).

### Claim 15 (depends on 11)

The method of claim 11, wherein the memory element is implemented with magnetoresistive random-access memory technology (MRAM).

### Claim 16 (depends on 11)

The method of claim 11, wherein the margin current branch comprises a control switch coupled to the sense amplifier circuit and configured to control flow of the margin current.

### Claim 17 (depends on 16)

The method of claim 16, wherein the control switch is configured to perform a logic check operation on the memory element by adding the margin current to the sense current during the sense operation.

### Claim 18 (depends on 11)

The method of claim 11, wherein the memory element is flagged with an error value when the sense operation has a different output value when the margin current is added.

### Claim 19 (depends on 11)

The method of claim 11, wherein the margin current branch comprises a plurality of current sources.

### Claim 20

A method for checking and refreshing a memory comprising a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element, wherein the memory element comprises a phase change material (PCM) or a first variable resistance, or wherein the memory element is implemented with resistive random-access memory technology (RRAM) or magnetoresistive random-access memory technology (MRAM), the method comprising:
during the sense operation, using the margin current branch to selectively add a margin current to the sense current.

### Claim 21 (depends on 20)

The method of claim 20, wherein the memory element comprises a phase change material (PCM).

### Claim 22 (depends on 20)

The method of claim 20, wherein the memory element comprises a first variable resistance.

### Claim 23 (depends on 20)

The method of claim 20, wherein the memory element is implemented with resistive random-access memory technology (RRAM).

### Claim 24 (depends on 20)

The method of claim 20, wherein the memory element is implemented with magnetoresistive random-access memory technology (MRAM).

### Claim 25

A method for checking and refreshing a memory comprising a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element, the method comprising:
during the sense operation, using the margin current branch to selectively add a margin current to the sense current; and
controlling a flow of the margin current with a control switch of the margin current branch, wherein the control switch is coupled to the sense amplifier circuit.

### Claim 26 (depends on 25)

The method of claim 25, further comprising performing a logic check operation on the memory element by adding the margin current to the sense current during the sense operation using the control switch.

### Claim 27

A method for checking and refreshing a memory comprising a memory element, a sense amplifier circuit configured to sense a difference during a sense operation between a sense current passing through the memory element and a reference current, and a margin current branch coupled in parallel with the memory element, the method comprising:
during the sense operation, using the margin current branch to selectively add a margin current to the sense current; and
flagging the memory element with an error value when the sense operation has a different output value when the margin current is added.

### Claim 28 (depends on 20)

The method of claim 20, wherein the margin current branch comprises a plurality of current sources.

### Claim 29 (depends on 7)

The memory of claim 7, wherein the memory element comprises a floating gate transistor.

### Claim 30 (depends on 7)

The memory of claim 7, wherein the memory element comprises a phase change material (PCM) or a first variable resistance, or wherein the memory element is implemented with resistive random-access memory technology (RRAM) or magnetoresistive random-access memory technology (MRAM).

### Claim 31 (depends on 8)

The memory of claim 8, wherein the memory element comprises a phase change material (PCM) or a first variable resistance, or wherein the memory element is implemented with resistive random-access memory technology (RRAM) or magnetoresistive random-access memory technology (MRAM).

### Claim 32 (depends on 10)

The memory of claim 10, wherein the memory element comprises a phase change material (PCM) or a first variable resistance, or wherein the memory element is implemented with resistive random-access memory technology (RRAM) or magnetoresistive random-access memory technology (MRAM).

### Claim 33 (depends on 25)

The method of claim 25, wherein the memory element comprises a phase change material (PCM) or a first variable resistance, or wherein the memory element is implemented with resistive random-access memory technology (RRAM) or magnetoresistive random-access memory technology (MRAM).

### Claim 34 (depends on 27)

The method of claim 27, wherein the memory element comprises a phase change material (PCM) or a first variable resistance, or wherein the memory element is implemented with resistive random-access memory technology (RRAM) or magnetoresistive random-access memory technology (MRAM).

### Claim 35 (depends on 27)

The method of claim 27, wherein the memory element comprises a floating gate transistor.